The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Baru-baru ini, pelbagai jenis peranti memori tak meruap (NVM) 3-D telah dikaji untuk meningkatkan ketumpatan integrasi [1]-[3]. Peranti NVM struktur tiang boleh dianggap sebagai salah satu calon [4], [5]. Apabila ini digunakan pada tatasusunan memori denyar NAND, hujung bawah saluran peranti disambungkan kepada silikon pukal. Dalam kes ini, arus dalam arah menegak berbeza-beza bergantung pada ketebalan saluran silikon. Apabila saluran tebal, perbezaan tahap arus tepu antara keadaan hidup/mati peranti individu adalah lebih jelas. Sebaliknya, apabila saluran nipis, arus hidup/mati meningkat secara serentak manakala arus tepu tidak banyak berbeza. Sebabnya ialah halangan potensi saluran yang dilihat oleh elektron longkang diturunkan oleh voltan baca pada pintu kawalan dinding sisi bertentangan. Fenomena ini yang boleh berlaku dalam peranti struktur 3-D kerana kedekatan boleh dipanggil pengurangan halangan akibat pintu (GIBL). Dalam kerja ini, pergantungan GIBL pada ketebalan saluran silikon disiasat, yang akan menjadi kriteria dalam pelaksanaan peranti NVM ultra-kecil yang boleh dipercayai.
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Salinan
Seongjae CHO, Jung Hoon LEE, Gil Sung LEE, Jong Duk LEE, Hyungcheol SHIN, Byung-Gook PARK, "Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 5, pp. 620-626, May 2009, doi: 10.1587/transele.E92.C.620.
Abstract: Recently, various types of 3-D nonvolatile memory (NVM) devices have been researched to improve the integration density [1]-[3]. The NVM device of pillar structure can be considered as one of the candidates [4],[5]. When this is applied to a NAND flash memory array, bottom end of the device channel is connected to the bulk silicon. In this case, the current in vertical direction varies depending on the thickness of silicon channel. When the channel is thick, the difference of saturation current levels between on/off states of individual device is more obvious. On the other hand, when the channel is thin, the on/off current increases simultaneously whereas the saturation currents do not differ very much. The reason is that the channel potential barrier seen by drain electrons is lowered by read voltage on the opposite sidewall control gate. This phenomenon that can occur in 3-D structure devices due to proximity can be called gate-induced barrier lowering (GIBL). In this work, the dependence of GIBL on silicon channel thickness is investigated, which will be the criteria in the implementation of reliable ultra-small NVM devices.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.620/_p
Salinan
@ARTICLE{e92-c_5_620,
author={Seongjae CHO, Jung Hoon LEE, Gil Sung LEE, Jong Duk LEE, Hyungcheol SHIN, Byung-Gook PARK, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)},
year={2009},
volume={E92-C},
number={5},
pages={620-626},
abstract={Recently, various types of 3-D nonvolatile memory (NVM) devices have been researched to improve the integration density [1]-[3]. The NVM device of pillar structure can be considered as one of the candidates [4],[5]. When this is applied to a NAND flash memory array, bottom end of the device channel is connected to the bulk silicon. In this case, the current in vertical direction varies depending on the thickness of silicon channel. When the channel is thick, the difference of saturation current levels between on/off states of individual device is more obvious. On the other hand, when the channel is thin, the on/off current increases simultaneously whereas the saturation currents do not differ very much. The reason is that the channel potential barrier seen by drain electrons is lowered by read voltage on the opposite sidewall control gate. This phenomenon that can occur in 3-D structure devices due to proximity can be called gate-induced barrier lowering (GIBL). In this work, the dependence of GIBL on silicon channel thickness is investigated, which will be the criteria in the implementation of reliable ultra-small NVM devices.},
keywords={},
doi={10.1587/transele.E92.C.620},
ISSN={1745-1353},
month={May},}
Salinan
TY - JOUR
TI - Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
T2 - IEICE TRANSACTIONS on Electronics
SP - 620
EP - 626
AU - Seongjae CHO
AU - Jung Hoon LEE
AU - Gil Sung LEE
AU - Jong Duk LEE
AU - Hyungcheol SHIN
AU - Byung-Gook PARK
PY - 2009
DO - 10.1587/transele.E92.C.620
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2009
AB - Recently, various types of 3-D nonvolatile memory (NVM) devices have been researched to improve the integration density [1]-[3]. The NVM device of pillar structure can be considered as one of the candidates [4],[5]. When this is applied to a NAND flash memory array, bottom end of the device channel is connected to the bulk silicon. In this case, the current in vertical direction varies depending on the thickness of silicon channel. When the channel is thick, the difference of saturation current levels between on/off states of individual device is more obvious. On the other hand, when the channel is thin, the on/off current increases simultaneously whereas the saturation currents do not differ very much. The reason is that the channel potential barrier seen by drain electrons is lowered by read voltage on the opposite sidewall control gate. This phenomenon that can occur in 3-D structure devices due to proximity can be called gate-induced barrier lowering (GIBL). In this work, the dependence of GIBL on silicon channel thickness is investigated, which will be the criteria in the implementation of reliable ultra-small NVM devices.
ER -