The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Satu 150 MS/s 10-bit MOS-inverter berasaskan subranging analog-to-digital converter (ADC) khusus untuk aplikasi kuasa rendah berkelajuan tinggi dibentangkan dalam kertas ini. Teknik pengurangan pemalar masa baharu dicadangkan dalam reka bentuk prapenguat berbilang peringkat yang bertujuan untuk meningkatkan lagi kelajuan ADC kasar. Suis disegerakkan diperkenalkan untuk meminimumkan ketidakpadanan masa sampel dalam seni bina bersilang ADC halus. Skim saluran paip dalaman yang menggabungkan teknik pensampelan berganda dan interleaving dalam ADC halus membolehkan isyarat input sampel ADC berjalan pada jam berturut-turut, sekali gus memaksimumkan daya pemprosesan. Prototaip ADC mencapai 52 dB SNDR untuk frekuensi input 10 MHz pada 150 MS/s. Tanpa penentukuran, ketaklinieran pembezaan terukur (DNL) ialah 0.5 LSB, manakala ketaklinieran kamiran (INL) ialah 0.9 LSB. ADC CMOS dibuat dalam teknologi CMOS 0.35 µm, dengan kawasan aktif 2.7 mm2, menggunakan hanya 178 mW daripada satu bekalan 3 V. Membandingkan angka merit yang dinormalkan oleh teknologi, ia mencapai kecekapan kelajuan kuasa yang lebih baik daripada jenis ADC lain yang serupa.
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Salinan
Xian Ping FAN, Pak Kwong CHAN, Piew Yoong CHEE, "A 150 MS/s 10-bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 5, pp. 719-727, May 2009, doi: 10.1587/transele.E92.C.719.
Abstract: A 150 MS/s 10-bit MOS-inverter-based subranging analog-to-digital converter (ADC) dedicated to a high-speed low-power application is presented in this paper. A new time constant reduction technique is proposed in the multi-stage preamplifier design which aims to further increase the speed of the coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatch in the interleaved architecture of fine ADCs. An internal pipelined scheme incorporating the double sampling and interleaving techniques in fine ADCs allows the ADC sample input signal to run on a consecutive clock, thus maximizing the throughput. The prototype ADC achieves 52 dB SNDR for a 10 MHz input frequency at 150 MS/s. Without calibration, the measured differential nonlinearity (DNL) is 0.5 LSB, while the integral nonlinearity (INL) is 0.9 LSB. The CMOS ADC is fabricated in a 0.35 µm CMOS technology, with an active area of 2.7 mm2, consuming only 178 mW from a single 3 V supply. Comparing technology normalized figure-of-merits, it achieves better power-speed efficiency than other similar types of ADCs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.719/_p
Salinan
@ARTICLE{e92-c_5_719,
author={Xian Ping FAN, Pak Kwong CHAN, Piew Yoong CHEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 150 MS/s 10-bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique},
year={2009},
volume={E92-C},
number={5},
pages={719-727},
abstract={A 150 MS/s 10-bit MOS-inverter-based subranging analog-to-digital converter (ADC) dedicated to a high-speed low-power application is presented in this paper. A new time constant reduction technique is proposed in the multi-stage preamplifier design which aims to further increase the speed of the coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatch in the interleaved architecture of fine ADCs. An internal pipelined scheme incorporating the double sampling and interleaving techniques in fine ADCs allows the ADC sample input signal to run on a consecutive clock, thus maximizing the throughput. The prototype ADC achieves 52 dB SNDR for a 10 MHz input frequency at 150 MS/s. Without calibration, the measured differential nonlinearity (DNL) is 0.5 LSB, while the integral nonlinearity (INL) is 0.9 LSB. The CMOS ADC is fabricated in a 0.35 µm CMOS technology, with an active area of 2.7 mm2, consuming only 178 mW from a single 3 V supply. Comparing technology normalized figure-of-merits, it achieves better power-speed efficiency than other similar types of ADCs.},
keywords={},
doi={10.1587/transele.E92.C.719},
ISSN={1745-1353},
month={May},}
Salinan
TY - JOUR
TI - A 150 MS/s 10-bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique
T2 - IEICE TRANSACTIONS on Electronics
SP - 719
EP - 727
AU - Xian Ping FAN
AU - Pak Kwong CHAN
AU - Piew Yoong CHEE
PY - 2009
DO - 10.1587/transele.E92.C.719
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2009
AB - A 150 MS/s 10-bit MOS-inverter-based subranging analog-to-digital converter (ADC) dedicated to a high-speed low-power application is presented in this paper. A new time constant reduction technique is proposed in the multi-stage preamplifier design which aims to further increase the speed of the coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatch in the interleaved architecture of fine ADCs. An internal pipelined scheme incorporating the double sampling and interleaving techniques in fine ADCs allows the ADC sample input signal to run on a consecutive clock, thus maximizing the throughput. The prototype ADC achieves 52 dB SNDR for a 10 MHz input frequency at 150 MS/s. Without calibration, the measured differential nonlinearity (DNL) is 0.5 LSB, while the integral nonlinearity (INL) is 0.9 LSB. The CMOS ADC is fabricated in a 0.35 µm CMOS technology, with an active area of 2.7 mm2, consuming only 178 mW from a single 3 V supply. Comparing technology normalized figure-of-merits, it achieves better power-speed efficiency than other similar types of ADCs.
ER -