The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Penukar analog-ke-digital (ADC) selang masa (TI) sering dianjurkan sebagai penyelesaian cekap kuasa untuk merealisasikan kadar pensampelan tinggi yang diperlukan dalam transceiver cip tunggal untuk skim komunikasi yang muncul: jalur lebar ultra, pautan bersiri pantas, radio kognitif dan radio yang ditakrifkan perisian. Walau bagaimanapun, kesan gabungan berbilang sumber herotan akibat ketidakpadanan saluran (lebar jalur, mengimbangi, keuntungan dan pemasaan) menjejaskan prestasi sistem dan penggunaan kuasa TI ADC dengan teruk dan perlu diambil kira sejak fasa reka bentuk yang lebih awal. Dalam kertas kerja ini, reka bentuk peringkat sistem TI ADC ditangani melalui metodologi berasaskan platform, membolehkan penyiasatan berkesan terhadap senario kelajuan/resolusi yang berbeza serta kesan selari pada ketepatan, hasil, kadar pensampelan, kawasan dan penggunaan kuasa. Penerokaan ruang reka bentuk ADC anggaran berturut-turut TI dilakukan dari atas ke bawah melalui simulasi Monte Carlo, dengan mengeksploitasi model tingkah laku yang dibina dari bawah ke atas selepas mencirikan pelaksanaan yang boleh dilaksanakan bagi blok binaan utama dalam proses CMOS 90-nm 1-V. Akibatnya, dua pelaksanaan TI ADC dicadangkan yang mampu memberikan angka merit yang cemerlang di bawah 0.15 pJ/langkah penukaran.
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Salinan
Sergio SAPONARA, Pierluigi NUZZO, Claudio NANI, Geert VAN DER PLAS, Luca FANUCCI, "Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 6, pp. 843-851, June 2009, doi: 10.1587/transele.E92.C.843.
Abstract: Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-efficient solution to realize the high sampling rates required in single-chip transceivers for the emerging communication schemes: ultra-wideband, fast serial links, cognitive-radio and software-defined radio. However, the combined effects of multiple distortion sources due to channel mismatches (bandwidth, offset, gain and timing) severely affect system performance and power consumption of a TI ADC and need to be accounted for since the earlier design phases. In this paper, system-level design of TI ADCs is addressed through a platform-based methodology, enabling effective investigation of different speed/resolution scenarios as well as the impact of parallelism on accuracy, yield, sampling-rate, area and power consumption. Design space exploration of a TI successive approximation ADC is performed top-down via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing feasible implementations of the main building blocks in a 90-nm 1-V CMOS process. As a result, two implementations of the TI ADC are proposed that are capable to provide an outstanding figure-of-merit below 0.15 pJ/conversion-step.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.843/_p
Salinan
@ARTICLE{e92-c_6_843,
author={Sergio SAPONARA, Pierluigi NUZZO, Claudio NANI, Geert VAN DER PLAS, Luca FANUCCI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters},
year={2009},
volume={E92-C},
number={6},
pages={843-851},
abstract={Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-efficient solution to realize the high sampling rates required in single-chip transceivers for the emerging communication schemes: ultra-wideband, fast serial links, cognitive-radio and software-defined radio. However, the combined effects of multiple distortion sources due to channel mismatches (bandwidth, offset, gain and timing) severely affect system performance and power consumption of a TI ADC and need to be accounted for since the earlier design phases. In this paper, system-level design of TI ADCs is addressed through a platform-based methodology, enabling effective investigation of different speed/resolution scenarios as well as the impact of parallelism on accuracy, yield, sampling-rate, area and power consumption. Design space exploration of a TI successive approximation ADC is performed top-down via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing feasible implementations of the main building blocks in a 90-nm 1-V CMOS process. As a result, two implementations of the TI ADC are proposed that are capable to provide an outstanding figure-of-merit below 0.15 pJ/conversion-step.},
keywords={},
doi={10.1587/transele.E92.C.843},
ISSN={1745-1353},
month={June},}
Salinan
TY - JOUR
TI - Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters
T2 - IEICE TRANSACTIONS on Electronics
SP - 843
EP - 851
AU - Sergio SAPONARA
AU - Pierluigi NUZZO
AU - Claudio NANI
AU - Geert VAN DER PLAS
AU - Luca FANUCCI
PY - 2009
DO - 10.1587/transele.E92.C.843
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2009
AB - Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-efficient solution to realize the high sampling rates required in single-chip transceivers for the emerging communication schemes: ultra-wideband, fast serial links, cognitive-radio and software-defined radio. However, the combined effects of multiple distortion sources due to channel mismatches (bandwidth, offset, gain and timing) severely affect system performance and power consumption of a TI ADC and need to be accounted for since the earlier design phases. In this paper, system-level design of TI ADCs is addressed through a platform-based methodology, enabling effective investigation of different speed/resolution scenarios as well as the impact of parallelism on accuracy, yield, sampling-rate, area and power consumption. Design space exploration of a TI successive approximation ADC is performed top-down via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing feasible implementations of the main building blocks in a 90-nm 1-V CMOS process. As a result, two implementations of the TI ADC are proposed that are capable to provide an outstanding figure-of-merit below 0.15 pJ/conversion-step.
ER -