The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam makalah ini, kami membentangkan teknik reka bentuk litar transistor komposit baharu yang memberikan peningkatan prestasi unggul kepada litar analog. Dengan menambahkan transistor komposit pada penguat berkompensasi cascode, ia telah mencapai keuntungan DC 102 dB, dan lebar jalur perolehan perpaduan 37.6 MHz semasa memacu beban kapasitif berat 2 nF pada bekalan 1.8 V tunggal. Dalam perbandingan lebar jalur kuasa dan kecekapan kelajuan kuasa pada angka merit, ia menawarkan nilai tinggi yang ketara berkenaan dengan karya terkini yang dilaporkan. Dengan menggunakan transistor komposit dalam pengawal selia linear yang dikuasakan oleh bekalan 3.3 V untuk menjana voltan keluaran 1.8 V, ia telah menunjukkan tindak balas pemulihan pantas pada pelbagai transien arus beban, mempunyai masa penyelesaian 1% sebanyak 0.1 µS untuk 50 mA atau 100 Langkah mA, manakala masa penyelesaian 1% 0.36 µS untuk langkah maksimum 735 mA di bawah beban kapasitif 10 µF dengan perintang 1 Ω ESR. Peraturan beban simulasi ialah 0.035% dan peraturan talian ialah 0.488%. Membandingkan keputusannya dengan keputusan terkini LDO yang dilaporkan, ia juga mengesahkan prestasi dipertingkatkan yang ketara bagi reka bentuk berasaskan transistor komposit yang dicadangkan dari segi kelajuan, keupayaan pemanduan semasa dan kestabilan terhadap perubahan dalam parameter persekitaran. Semua reka bentuk yang dicadangkan disimulasikan menggunakan semikonduktor bercarter (CSM) 1.8 V/3.3 V 0.18 µm teknologi proses tiga telaga CMOS dengan pilihan oksida nipis/tebal dan parameter model BSIM3.
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Salinan
Yang TIAN, Pak Kwong CHAN, "Design of High-Performance Analog Circuits Using Wideband gm-Enhanced MOS Composite Transistors" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 7, pp. 1199-1208, July 2010, doi: 10.1587/transele.E93.C.1199.
Abstract: In this paper, we present a new composite transistor circuit design technique that provides superior performance enhancement to analog circuits. By adding a composite transistor to the cascode-compensated amplifier, it has achieved a 102 dB DC gain, and a 37.6 MHz unity gain bandwidth while driving a 2 nF heavy capacitive load at a single 1.8 V supply. In the comparison of power-bandwidth and power-speed efficiencies on figures of merit, it offers significantly high values with respect to the reported state-of-the-art works. By employing the composite transistor in a linear regulator powered by a 3.3 V supply to generate a 1.8 V output voltage, it has shown fast recovery response at various load current transients, having a 1% settling time of 0.1 µS for a 50 mA or 100 mA step, while a 1% settling time of 0.36 µS for a maximum 735 mA step under a capacitive load of 10 µF with a 1 Ω ESR resistor. The simulated load regulation is 0.035% and line regulation is 0.488%. Comparing its results with other state-of-art LDO reported results, it also validates the significant enhanced performance of the proposed composite-transistor-based design in terms of speed, current driving capability and stability against changes in environmental parameters. All the proposed designs are simulated using chartered semiconductor (CSM) 1.8 V/3.3 V 0.18 µm CMOS triple-well process technology with thin/thick oxide options and BSIM3 model parameters.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.1199/_p
Salinan
@ARTICLE{e93-c_7_1199,
author={Yang TIAN, Pak Kwong CHAN, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of High-Performance Analog Circuits Using Wideband gm-Enhanced MOS Composite Transistors},
year={2010},
volume={E93-C},
number={7},
pages={1199-1208},
abstract={In this paper, we present a new composite transistor circuit design technique that provides superior performance enhancement to analog circuits. By adding a composite transistor to the cascode-compensated amplifier, it has achieved a 102 dB DC gain, and a 37.6 MHz unity gain bandwidth while driving a 2 nF heavy capacitive load at a single 1.8 V supply. In the comparison of power-bandwidth and power-speed efficiencies on figures of merit, it offers significantly high values with respect to the reported state-of-the-art works. By employing the composite transistor in a linear regulator powered by a 3.3 V supply to generate a 1.8 V output voltage, it has shown fast recovery response at various load current transients, having a 1% settling time of 0.1 µS for a 50 mA or 100 mA step, while a 1% settling time of 0.36 µS for a maximum 735 mA step under a capacitive load of 10 µF with a 1 Ω ESR resistor. The simulated load regulation is 0.035% and line regulation is 0.488%. Comparing its results with other state-of-art LDO reported results, it also validates the significant enhanced performance of the proposed composite-transistor-based design in terms of speed, current driving capability and stability against changes in environmental parameters. All the proposed designs are simulated using chartered semiconductor (CSM) 1.8 V/3.3 V 0.18 µm CMOS triple-well process technology with thin/thick oxide options and BSIM3 model parameters.},
keywords={},
doi={10.1587/transele.E93.C.1199},
ISSN={1745-1353},
month={July},}
Salinan
TY - JOUR
TI - Design of High-Performance Analog Circuits Using Wideband gm-Enhanced MOS Composite Transistors
T2 - IEICE TRANSACTIONS on Electronics
SP - 1199
EP - 1208
AU - Yang TIAN
AU - Pak Kwong CHAN
PY - 2010
DO - 10.1587/transele.E93.C.1199
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2010
AB - In this paper, we present a new composite transistor circuit design technique that provides superior performance enhancement to analog circuits. By adding a composite transistor to the cascode-compensated amplifier, it has achieved a 102 dB DC gain, and a 37.6 MHz unity gain bandwidth while driving a 2 nF heavy capacitive load at a single 1.8 V supply. In the comparison of power-bandwidth and power-speed efficiencies on figures of merit, it offers significantly high values with respect to the reported state-of-the-art works. By employing the composite transistor in a linear regulator powered by a 3.3 V supply to generate a 1.8 V output voltage, it has shown fast recovery response at various load current transients, having a 1% settling time of 0.1 µS for a 50 mA or 100 mA step, while a 1% settling time of 0.36 µS for a maximum 735 mA step under a capacitive load of 10 µF with a 1 Ω ESR resistor. The simulated load regulation is 0.035% and line regulation is 0.488%. Comparing its results with other state-of-art LDO reported results, it also validates the significant enhanced performance of the proposed composite-transistor-based design in terms of speed, current driving capability and stability against changes in environmental parameters. All the proposed designs are simulated using chartered semiconductor (CSM) 1.8 V/3.3 V 0.18 µm CMOS triple-well process technology with thin/thick oxide options and BSIM3 model parameters.
ER -