The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kami mencipta IC pemultipleks 2:1 (MUX) dengan fungsi retiming dengan menggunakan transistor bipolar (DHBT) penjajaran kendiri 1-µm InP/InGaAs/InP dengan tebing pempasifan mesa pemancar. MUX beroperasi pada 120 Gbit/s dengan pelesapan kuasa 1.27 W dan amplitud keluaran 520 mV apabila diukur pada wafer. Apabila dipasang dalam modul menggunakan penyambung V, MUX beroperasi pada 113 Gbit/s dengan amplitud keluaran 514-mV dan pelesapan kuasa 1.4 W.
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Salinan
Yutaka ARAYASHIKI, Yukio OHKUBO, Taisuke MATSUMOTO, Yoshiaki AMANO, Akio TAKAGI, Yutaka MATSUOKA, "A 120-Gbit/s 1.27-W 520-mVpp 2:1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 8, pp. 1273-1278, August 2010, doi: 10.1587/transele.E93.C.1273.
Abstract: We fabricated a 2:1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120 Gbit/s with a power dissipation of 1.27 W and output amplitude of 520 mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113 Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4 W.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.1273/_p
Salinan
@ARTICLE{e93-c_8_1273,
author={Yutaka ARAYASHIKI, Yukio OHKUBO, Taisuke MATSUMOTO, Yoshiaki AMANO, Akio TAKAGI, Yutaka MATSUOKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 120-Gbit/s 1.27-W 520-mVpp 2:1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation},
year={2010},
volume={E93-C},
number={8},
pages={1273-1278},
abstract={We fabricated a 2:1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120 Gbit/s with a power dissipation of 1.27 W and output amplitude of 520 mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113 Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4 W.},
keywords={},
doi={10.1587/transele.E93.C.1273},
ISSN={1745-1353},
month={August},}
Salinan
TY - JOUR
TI - A 120-Gbit/s 1.27-W 520-mVpp 2:1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation
T2 - IEICE TRANSACTIONS on Electronics
SP - 1273
EP - 1278
AU - Yutaka ARAYASHIKI
AU - Yukio OHKUBO
AU - Taisuke MATSUMOTO
AU - Yoshiaki AMANO
AU - Akio TAKAGI
AU - Yutaka MATSUOKA
PY - 2010
DO - 10.1587/transele.E93.C.1273
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2010
AB - We fabricated a 2:1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120 Gbit/s with a power dissipation of 1.27 W and output amplitude of 520 mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113 Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4 W.
ER -