The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Model padat sedar reka letak yang dicadangkan setakat ini telah disahkan secara amnya hanya untuk corak ujian mudah. Walau bagaimanapun, reka bentuk sebenar menggunakan corak susun atur yang lebih rumit. Oleh itu, model mesti disahkan untuk corak sedemikian untuk mewujudkan kepraktisan mereka. Kertas kerja ini mencadangkan metodologi dan corak ujian untuk mengesahkan model kompak yang sedar susun atur secara menyeluruh dan sistematik untuk corak susun atur umum buat kali pertama. Metodologi dan corak ujian ditunjukkan secara konkrit melalui pengesahan model padat tegasan pengasingan parit cetek (STI) yang dicadangkan dalam [1]. Mula-mula, parameter model untuk teknologi CMOS 55-nm diekstrak, dan kemudian model itu disahkan dan diwujudkan agar tepat untuk corak asas yang digunakan untuk pengekstrakan parameter. Seterusnya, idea asas operasi model untuk corak susun atur umum disahkan menggunakan pelbagai corak pengesahan. Ujian ini mendedahkan bahawa model itu agak lemah dalam beberapa kes tidak termasuk dalam corak asas. Akhirnya, ralat untuk kes ini dihapuskan dengan meningkatkan algoritma. Akibatnya, model itu disahkan mempunyai keluasan yang tinggi. Metodologi ini akan berkesan untuk mengesahkan model padat yang menyedari reka letak lain untuk corak susun atur umum.
Kenta YAMADA
Toshiyuki SYO
Hisao YOSHIMURA
Masaru ITO
Tatsuya KUNIKIYO
Toshiki KANAMOTO
Shigetaka KUMASHIRO
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Salinan
Kenta YAMADA, Toshiyuki SYO, Hisao YOSHIMURA, Masaru ITO, Tatsuya KUNIKIYO, Toshiki KANAMOTO, Shigetaka KUMASHIRO, "Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 8, pp. 1349-1358, August 2010, doi: 10.1587/transele.E93.C.1349.
Abstract: Layout-aware compact models proposed so far have been generally verified only for simple test patterns. However, real designs use much more complicated layout patterns. Therefore, models must be verified for such patterns to establish their practicality. This paper proposes a methodology and test patterns for exhaustively and systematically validating layout-aware compact models for general layout patterns for the first time. The methodology and test patterns are concretely shown through validation of a shallow trench isolation (STI) stress compact model proposed in [1]. First, the model parameters for a 55-nm CMOS technology are extracted, and then the model is verified and established to be accurate for the basic patterns used for parameter extraction. Next, fundamental ideas of model operation for general layout patterns are verified using various verification patterns. These tests revealed that the model is relatively weak in some cases not included in the basic patterns. Finally, the errors for these cases are eliminated by enhancing the algorithm. Consequently, the model is confirmed to have high generality. This methodology will be effective for validating other layout-aware compact models for general layout patterns.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.1349/_p
Salinan
@ARTICLE{e93-c_8_1349,
author={Kenta YAMADA, Toshiyuki SYO, Hisao YOSHIMURA, Masaru ITO, Tatsuya KUNIKIYO, Toshiki KANAMOTO, Shigetaka KUMASHIRO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns},
year={2010},
volume={E93-C},
number={8},
pages={1349-1358},
abstract={Layout-aware compact models proposed so far have been generally verified only for simple test patterns. However, real designs use much more complicated layout patterns. Therefore, models must be verified for such patterns to establish their practicality. This paper proposes a methodology and test patterns for exhaustively and systematically validating layout-aware compact models for general layout patterns for the first time. The methodology and test patterns are concretely shown through validation of a shallow trench isolation (STI) stress compact model proposed in [1]. First, the model parameters for a 55-nm CMOS technology are extracted, and then the model is verified and established to be accurate for the basic patterns used for parameter extraction. Next, fundamental ideas of model operation for general layout patterns are verified using various verification patterns. These tests revealed that the model is relatively weak in some cases not included in the basic patterns. Finally, the errors for these cases are eliminated by enhancing the algorithm. Consequently, the model is confirmed to have high generality. This methodology will be effective for validating other layout-aware compact models for general layout patterns.},
keywords={},
doi={10.1587/transele.E93.C.1349},
ISSN={1745-1353},
month={August},}
Salinan
TY - JOUR
TI - Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns
T2 - IEICE TRANSACTIONS on Electronics
SP - 1349
EP - 1358
AU - Kenta YAMADA
AU - Toshiyuki SYO
AU - Hisao YOSHIMURA
AU - Masaru ITO
AU - Tatsuya KUNIKIYO
AU - Toshiki KANAMOTO
AU - Shigetaka KUMASHIRO
PY - 2010
DO - 10.1587/transele.E93.C.1349
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2010
AB - Layout-aware compact models proposed so far have been generally verified only for simple test patterns. However, real designs use much more complicated layout patterns. Therefore, models must be verified for such patterns to establish their practicality. This paper proposes a methodology and test patterns for exhaustively and systematically validating layout-aware compact models for general layout patterns for the first time. The methodology and test patterns are concretely shown through validation of a shallow trench isolation (STI) stress compact model proposed in [1]. First, the model parameters for a 55-nm CMOS technology are extracted, and then the model is verified and established to be accurate for the basic patterns used for parameter extraction. Next, fundamental ideas of model operation for general layout patterns are verified using various verification patterns. These tests revealed that the model is relatively weak in some cases not included in the basic patterns. Finally, the errors for these cases are eliminated by enhancing the algorithm. Consequently, the model is confirmed to have high generality. This methodology will be effective for validating other layout-aware compact models for general layout patterns.
ER -