The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini membentangkan VLSI sensor-nod cip tunggal ultra-rendah untuk aplikasi rangkaian-sensor wayarles. Pendekatan reka bentuk berpusatkan komunikasi telah diperkenalkan untuk mengurangkan penggunaan kuasa litar RF dan keseluruhan sistem rangkaian sensor, melalui reka bentuk koperasi menegak antara litar, seni bina dan protokol komunikasi. LSI nod sensor mempunyai protokol kawalan akses media (MAC) segerak dan menyepadukan transceiver, mikropengawal i8051 dan pemproses MAC khusus. Cip ujian menduduki 3
Shintaro IZUMI
Takashi TAKEUCHI
Takashi MATSUDA
Hyeokjong LEE
Toshihiro KONISHI
Koh TSURUDA
Yasuharu SAKAI
Hiroshi KAWAGUCHI
Chikara OHTA
Masahiko YOSHIMOTO
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Salinan
Shintaro IZUMI, Takashi TAKEUCHI, Takashi MATSUDA, Hyeokjong LEE, Toshihiro KONISHI, Koh TSURUDA, Yasuharu SAKAI, Hiroshi KAWAGUCHI, Chikara OHTA, Masahiko YOSHIMOTO, "A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 3, pp. 261-269, March 2010, doi: 10.1587/transele.E93.C.261.
Abstract: This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications. A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver, i8051 microcontroller, and dedicated MAC processor. The test chip occupies 3
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.261/_p
Salinan
@ARTICLE{e93-c_3_261,
author={Shintaro IZUMI, Takashi TAKEUCHI, Takashi MATSUDA, Hyeokjong LEE, Toshihiro KONISHI, Koh TSURUDA, Yasuharu SAKAI, Hiroshi KAWAGUCHI, Chikara OHTA, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design},
year={2010},
volume={E93-C},
number={3},
pages={261-269},
abstract={This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications. A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver, i8051 microcontroller, and dedicated MAC processor. The test chip occupies 3
keywords={},
doi={10.1587/transele.E93.C.261},
ISSN={1745-1353},
month={March},}
Salinan
TY - JOUR
TI - A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 261
EP - 269
AU - Shintaro IZUMI
AU - Takashi TAKEUCHI
AU - Takashi MATSUDA
AU - Hyeokjong LEE
AU - Toshihiro KONISHI
AU - Koh TSURUDA
AU - Yasuharu SAKAI
AU - Hiroshi KAWAGUCHI
AU - Chikara OHTA
AU - Masahiko YOSHIMOTO
PY - 2010
DO - 10.1587/transele.E93.C.261
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2010
AB - This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications. A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver, i8051 microcontroller, and dedicated MAC processor. The test chip occupies 3
ER -