The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam kertas ini, sel Penambah Penuh CNFET berkelajuan ultra tinggi dibentangkan. Reka bentuk ini menghasilkan isyarat jumlah dan bawa keluar melalui gerbang majoriti dan bukan majoriti yang dilaksanakan oleh penimbal CNFET, penyongsang CNFET dan kapasitor input. Peningkatan ketara dari segi kelajuan dan Produk Kelewatan Kuasa (PDP) dicapai.
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Salinan
Keivan NAVI, Fazel SHARIFI, Amir MOMENI, Peiman KESHAVARZIAN, "Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 6, pp. 932-934, June 2010, doi: 10.1587/transele.E93.C.932.
Abstract: In this paper an ultra high speed CNFET Full-Adder cell is presented. This design generates sum and carry-out signals via majority and majority-not gates which are implemented by CNFET buffer, CNFET inverter and input capacitors. Significant improvement in terms of speed and Power-Delay Product (PDP) is achieved.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.932/_p
Salinan
@ARTICLE{e93-c_6_932,
author={Keivan NAVI, Fazel SHARIFI, Amir MOMENI, Peiman KESHAVARZIAN, },
journal={IEICE TRANSACTIONS on Electronics},
title={Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates},
year={2010},
volume={E93-C},
number={6},
pages={932-934},
abstract={In this paper an ultra high speed CNFET Full-Adder cell is presented. This design generates sum and carry-out signals via majority and majority-not gates which are implemented by CNFET buffer, CNFET inverter and input capacitors. Significant improvement in terms of speed and Power-Delay Product (PDP) is achieved.},
keywords={},
doi={10.1587/transele.E93.C.932},
ISSN={1745-1353},
month={June},}
Salinan
TY - JOUR
TI - Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates
T2 - IEICE TRANSACTIONS on Electronics
SP - 932
EP - 934
AU - Keivan NAVI
AU - Fazel SHARIFI
AU - Amir MOMENI
AU - Peiman KESHAVARZIAN
PY - 2010
DO - 10.1587/transele.E93.C.932
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2010
AB - In this paper an ultra high speed CNFET Full-Adder cell is presented. This design generates sum and carry-out signals via majority and majority-not gates which are implemented by CNFET buffer, CNFET inverter and input capacitors. Significant improvement in terms of speed and Power-Delay Product (PDP) is achieved.
ER -