The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam makalah ini, kami mencadangkan satu kaedah untuk sintesis pokok jam condong dipacu susun atur untuk litar logik SFQ. Untuk litar logik tertentu tanpa pokok jam, algoritma kami mengeluarkan litar dengan pepohon jam tersintesis dan pelarasan masa yang mencapai tempoh jam yang diberikan dan peletakan kasar get jam. Dalam algoritma yang dicadangkan, gerbang jam dikelompokkan ke dalam tahap dan pokok jam disintesis untuk setiap peringkat. Untuk setiap peringkat, kami menganggarkan pemasaan jam untuk semua kemungkinan penempatan setiap pintu, dan kemudian kami mencari penempatan semua pintu yang meminimumkan jumlah elemen kelewatan untuk pelarasan masa. Setelah penempatan diperoleh, kami mensintesis pokok jam tanpa persimpangan wayar. Kami menggunakan kaedah yang dicadangkan pada litar bersaiz sederhana dan mengesahkan bahawa pokok jam yang memenuhi keperluan pemasaan tertentu boleh disintesis secara automatik.
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Salinan
Kazuyoshi TAKAGI, Yuki ITO, Shota TAKESHIMA, Masamitsu TANAKA, Naofumi TAKAGI, "Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 3, pp. 288-295, March 2011, doi: 10.1587/transele.E94.C.288.
Abstract: In this paper, we propose a method for layout-driven skewed clock tree synthesis for SFQ logic circuits. For a given logic circuit without a clock tree, our algorithm outputs a circuit with a synthesized clock tree and timing adjustments achieving the given clock period and a rough placement of the clocked gates. In the proposed algorithm, clocked gates are grouped into levels and the clock tree is synthesized for each level. For each level, we estimate the clock timing for all possible placements of each gate, and then we search a placement of all gates that minimizes the total number of delay elements for timing adjustment. Once the placement is obtained, we synthesize a clock tree without wire intersections. We applied the proposed method to a moderate size circuit and confirmed that clock trees satisfying given timing requirements can be synthesized automatically.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.288/_p
Salinan
@ARTICLE{e94-c_3_288,
author={Kazuyoshi TAKAGI, Yuki ITO, Shota TAKESHIMA, Masamitsu TANAKA, Naofumi TAKAGI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits},
year={2011},
volume={E94-C},
number={3},
pages={288-295},
abstract={In this paper, we propose a method for layout-driven skewed clock tree synthesis for SFQ logic circuits. For a given logic circuit without a clock tree, our algorithm outputs a circuit with a synthesized clock tree and timing adjustments achieving the given clock period and a rough placement of the clocked gates. In the proposed algorithm, clocked gates are grouped into levels and the clock tree is synthesized for each level. For each level, we estimate the clock timing for all possible placements of each gate, and then we search a placement of all gates that minimizes the total number of delay elements for timing adjustment. Once the placement is obtained, we synthesize a clock tree without wire intersections. We applied the proposed method to a moderate size circuit and confirmed that clock trees satisfying given timing requirements can be synthesized automatically.},
keywords={},
doi={10.1587/transele.E94.C.288},
ISSN={1745-1353},
month={March},}
Salinan
TY - JOUR
TI - Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 288
EP - 295
AU - Kazuyoshi TAKAGI
AU - Yuki ITO
AU - Shota TAKESHIMA
AU - Masamitsu TANAKA
AU - Naofumi TAKAGI
PY - 2011
DO - 10.1587/transele.E94.C.288
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2011
AB - In this paper, we propose a method for layout-driven skewed clock tree synthesis for SFQ logic circuits. For a given logic circuit without a clock tree, our algorithm outputs a circuit with a synthesized clock tree and timing adjustments achieving the given clock period and a rough placement of the clocked gates. In the proposed algorithm, clocked gates are grouped into levels and the clock tree is synthesized for each level. For each level, we estimate the clock timing for all possible placements of each gate, and then we search a placement of all gates that minimizes the total number of delay elements for timing adjustment. Once the placement is obtained, we synthesize a clock tree without wire intersections. We applied the proposed method to a moderate size circuit and confirmed that clock trees satisfying given timing requirements can be synthesized automatically.
ER -