The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dengan kemunculan usia submikron dalam, prestasi litar sangat dipengaruhi oleh variasi proses dan pengaruh ke atas kelewatan litar kepada voltan bekalan kuasa semakin meningkat disebabkan oleh pengecutan saiz ciri CMOS. Pengoptimuman grid kuasa yang mempertimbangkan risiko ralat pemasaan yang disebabkan oleh variasi dan kejatuhan IR menjadi sangat penting untuk pengendalian sistem-pada-cip yang stabil dan berkelajuan tinggi. Secara konvensional, banyak algoritma pengoptimuman grid kuasa telah dicadangkan, dan kebanyakannya menggunakan penurunan IR sebagai fungsi objek mereka. Walau bagaimanapun, penurunan IR ialah metrik tidak langsung dan kami mengesyaki bahawa ia adalah metrik kabur untuk matlamat sebenar reka bentuk LSI. Dalam makalah ini, pertama, kami mencadangkan pendekatan yang menggunakan "risiko ralat masa yang disebabkan oleh penurunan IR" sebagai fungsi objektif langsung. Kedua, peta laluan kritikal diperkenalkan untuk menyatakan kewujudan laluan kritikal yang diedarkan dalam keseluruhan cip. Risiko ralat pemasaan dikurangkan dengan menggunakan peta laluan kritikal dan fungsi objektif baharu. Beberapa keputusan eksperimen menunjukkan keberkesanannya.
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Salinan
Yoshiyuki KAWAKAMI, Makoto TERAO, Masahiro FUKUI, Shuji TSUKIYAMA, "A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 12, pp. 3423-3430, December 2008, doi: 10.1093/ietfec/e91-a.12.3423.
Abstract: With the advent of the deep submicron age, circuit performance is strongly impacted by process variations and the influence on the circuit delay to the power-supply voltage increases more and more due to CMOS feature size shrinkage. Power grid optimization which considers the timing error risk caused by the variations and IR drop becomes very important for stable and hi-speed operation of system-on-chip. Conventionally, a lot of power grid optimization algorithms have been proposed, and most of them use IR drop as their object functions. However, the IR drop is an indirect metric and we suspect that it is vague metric for the real goal of LSI design. In this paper, first, we propose an approach which uses the "timing error risk caused by IR drop" as a direct objective function. Second, the critical path map is introduced to express the existence of critical paths distributed in the entire chip. The timing error risk is decreased by using the critical path map and the new objective function. Some experimental results show the effectiveness.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.12.3423/_p
Salinan
@ARTICLE{e91-a_12_3423,
author={Yoshiyuki KAWAKAMI, Makoto TERAO, Masahiro FUKUI, Shuji TSUKIYAMA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop},
year={2008},
volume={E91-A},
number={12},
pages={3423-3430},
abstract={With the advent of the deep submicron age, circuit performance is strongly impacted by process variations and the influence on the circuit delay to the power-supply voltage increases more and more due to CMOS feature size shrinkage. Power grid optimization which considers the timing error risk caused by the variations and IR drop becomes very important for stable and hi-speed operation of system-on-chip. Conventionally, a lot of power grid optimization algorithms have been proposed, and most of them use IR drop as their object functions. However, the IR drop is an indirect metric and we suspect that it is vague metric for the real goal of LSI design. In this paper, first, we propose an approach which uses the "timing error risk caused by IR drop" as a direct objective function. Second, the critical path map is introduced to express the existence of critical paths distributed in the entire chip. The timing error risk is decreased by using the critical path map and the new objective function. Some experimental results show the effectiveness.},
keywords={},
doi={10.1093/ietfec/e91-a.12.3423},
ISSN={1745-1337},
month={December},}
Salinan
TY - JOUR
TI - A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3423
EP - 3430
AU - Yoshiyuki KAWAKAMI
AU - Makoto TERAO
AU - Masahiro FUKUI
AU - Shuji TSUKIYAMA
PY - 2008
DO - 10.1093/ietfec/e91-a.12.3423
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2008
AB - With the advent of the deep submicron age, circuit performance is strongly impacted by process variations and the influence on the circuit delay to the power-supply voltage increases more and more due to CMOS feature size shrinkage. Power grid optimization which considers the timing error risk caused by the variations and IR drop becomes very important for stable and hi-speed operation of system-on-chip. Conventionally, a lot of power grid optimization algorithms have been proposed, and most of them use IR drop as their object functions. However, the IR drop is an indirect metric and we suspect that it is vague metric for the real goal of LSI design. In this paper, first, we propose an approach which uses the "timing error risk caused by IR drop" as a direct objective function. Second, the critical path map is introduced to express the existence of critical paths distributed in the entire chip. The timing error risk is decreased by using the critical path map and the new objective function. Some experimental results show the effectiveness.
ER -