The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini membentangkan pendekatan sintesis peringkat tinggi untuk meminimumkan jumlah penggunaan kuasa dalam sintesis tingkah laku di bawah kekangan masa dan kawasan. Kaedah yang dicadangkan mempunyai dua peringkat, pengoptimuman tenaga unit berfungsi (FU) dan pengoptimuman tenaga antara sambungan. Pada peringkat pertama, tenaga aktif dan tidak aktif FU dioptimumkan menggunakan skema voltan bekalan dan ambang berganda. Algoritma genetik (GA) penetapan serentak bekalan dan voltan ambang dan pemilihan modul dicadangkan. Kaedah carian berasaskan GA yang dicadangkan boleh digunakan dalam masalah saiz besar untuk mencari penyelesaian yang hampir optimum dalam masa yang munasabah. Pada peringkat kedua, interkoneksi dipermudahkan dengan meningkatkan perkongsian mereka. Ini dilakukan dengan mengeksploitasi corak pemindahan data yang serupa di kalangan FU. Kaedah yang dicadangkan dinilai untuk beberapa penanda aras di bawah teknologi CMOS 90 nm. Keputusan eksperimen menunjukkan bahawa lebih daripada 40% penjimatan tenaga boleh dicapai dengan kaedah yang dicadangkan kami.
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Salinan
Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA, "Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 12, pp. 3596-3606, December 2008, doi: 10.1093/ietfec/e91-a.12.3596.
Abstract: This paper presents a high-level synthesis approach to minimize the total power consumption in behavioral synthesis under time and area constraints. The proposed method has two stages, functional unit (FU) energy optimization and interconnect energy optimization. In the first stage, active and inactive energies of the FUs are optimized using a multiple supply and threshold voltage scheme. Genetic algorithm (GA) based simultaneous assignment of supply and threshold voltages and module selection is proposed. The proposed GA based searching method can be used in large size problems to find a near-optimal solution in a reasonable time. In the second stage, interconnects are simplified by increasing their sharing. This is done by exploiting similar data transfer patterns among FUs. The proposed method is evaluated for several benchmarks under 90 nm CMOS technology. The experimental results show that more than 40% of energy savings can be achieved by our proposed method.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.12.3596/_p
Salinan
@ARTICLE{e91-a_12_3596,
author={Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages},
year={2008},
volume={E91-A},
number={12},
pages={3596-3606},
abstract={This paper presents a high-level synthesis approach to minimize the total power consumption in behavioral synthesis under time and area constraints. The proposed method has two stages, functional unit (FU) energy optimization and interconnect energy optimization. In the first stage, active and inactive energies of the FUs are optimized using a multiple supply and threshold voltage scheme. Genetic algorithm (GA) based simultaneous assignment of supply and threshold voltages and module selection is proposed. The proposed GA based searching method can be used in large size problems to find a near-optimal solution in a reasonable time. In the second stage, interconnects are simplified by increasing their sharing. This is done by exploiting similar data transfer patterns among FUs. The proposed method is evaluated for several benchmarks under 90 nm CMOS technology. The experimental results show that more than 40% of energy savings can be achieved by our proposed method.},
keywords={},
doi={10.1093/ietfec/e91-a.12.3596},
ISSN={1745-1337},
month={December},}
Salinan
TY - JOUR
TI - Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3596
EP - 3606
AU - Hasitha Muthumala WAIDYASOORIYA
AU - Masanori HARIYAMA
AU - Michitaka KAMEYAMA
PY - 2008
DO - 10.1093/ietfec/e91-a.12.3596
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2008
AB - This paper presents a high-level synthesis approach to minimize the total power consumption in behavioral synthesis under time and area constraints. The proposed method has two stages, functional unit (FU) energy optimization and interconnect energy optimization. In the first stage, active and inactive energies of the FUs are optimized using a multiple supply and threshold voltage scheme. Genetic algorithm (GA) based simultaneous assignment of supply and threshold voltages and module selection is proposed. The proposed GA based searching method can be used in large size problems to find a near-optimal solution in a reasonable time. In the second stage, interconnects are simplified by increasing their sharing. This is done by exploiting similar data transfer patterns among FUs. The proposed method is evaluated for several benchmarks under 90 nm CMOS technology. The experimental results show that more than 40% of energy savings can be achieved by our proposed method.
ER -