The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Keluarga DRAM luar cip yang lebih baharu, termasuk DRAM Segerak (SDRAM) dan DRAM RAMBUS (RDRAM), menjadi pilihan standard untuk reka bentuk sistem berprestasi tinggi. Walaupun kerja sebelumnya dalam Sintesis Tahap Tinggi (HLS) telah menangani ciri mengeksploitasi DRAM mod halaman, teknik tidak wujud untuk mengeksploitasi dua ciri utama keluarga DRAM yang lebih baharu ini yang meningkatkan prestasi memori dan membantu mengatasi had lebar jalur: (1) pecah akses mod, dan (2) akses bersilang melalui berbilang bank. Kami menangani pengoptimuman pra-sintesis pada gelagat input yang mengekstrak dan mengeksploitasi mod pecah dan berbilang mod capaian bersilang bank bagi keluarga DRAM yang lebih baharu ini, supaya ciri ini boleh dieksploitasi sepenuhnya semasa trajektori HLS. Percubaan kami, dijalankan pada set penanda aras intensif memori menggunakan perpustakaan SDRAM kontemporari, menunjukkan peningkatan prestasi yang ketara sehingga 62.5% berbanding pendekatan naif dan peningkatan sehingga 16.7% berbanding pendekatan sebelumnya yang hanya mempertimbangkan mod halaman atau DRAM keluaran data lanjutan (EDO).
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Salinan
Asheesh KHARE, Preeti R. PANDA, Nikil D. DUTT, Alexandru NICOLAU, "High-Level Synthesis with SDRAMs and RAMBUS DRAMs" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2347-2355, November 1999, doi: .
Abstract: Newer off-chip DRAM families, including Synchronous DRAMs (SDRAMs) and RAMBUS DRAMs (RDRAMs), are becoming standard choices for the design of high-performance systems. Although previous work in High-Level Synthesis (HLS) has addressed exploiting features of page-mode DRAMs, techniques do not exist for exploiting the two key features of these newer DRAM families that boost memory performance and help overcome bandwidth limitations: (1) burst mode access, and (2) interleaved access through multiple banks. We address pre-synthesis optimizations on the input behavior that extract and exploit the burst mode and multiple bank interleaved access modes of these newer DRAM families, so that these features can be exploited fully during the HLS trajectory. Our experiments, run on a suite of memory-intensive benchmarks using a contemporary SDRAM library, demonstrate significant performance improvements of up to 62.5% over the naive approach, and improvements of up to 16.7% over the previous approach that considered only page-mode or extended-data-out (EDO) DRAMS.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2347/_p
Salinan
@ARTICLE{e82-a_11_2347,
author={Asheesh KHARE, Preeti R. PANDA, Nikil D. DUTT, Alexandru NICOLAU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Level Synthesis with SDRAMs and RAMBUS DRAMs},
year={1999},
volume={E82-A},
number={11},
pages={2347-2355},
abstract={Newer off-chip DRAM families, including Synchronous DRAMs (SDRAMs) and RAMBUS DRAMs (RDRAMs), are becoming standard choices for the design of high-performance systems. Although previous work in High-Level Synthesis (HLS) has addressed exploiting features of page-mode DRAMs, techniques do not exist for exploiting the two key features of these newer DRAM families that boost memory performance and help overcome bandwidth limitations: (1) burst mode access, and (2) interleaved access through multiple banks. We address pre-synthesis optimizations on the input behavior that extract and exploit the burst mode and multiple bank interleaved access modes of these newer DRAM families, so that these features can be exploited fully during the HLS trajectory. Our experiments, run on a suite of memory-intensive benchmarks using a contemporary SDRAM library, demonstrate significant performance improvements of up to 62.5% over the naive approach, and improvements of up to 16.7% over the previous approach that considered only page-mode or extended-data-out (EDO) DRAMS.},
keywords={},
doi={},
ISSN={},
month={November},}
Salinan
TY - JOUR
TI - High-Level Synthesis with SDRAMs and RAMBUS DRAMs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2347
EP - 2355
AU - Asheesh KHARE
AU - Preeti R. PANDA
AU - Nikil D. DUTT
AU - Alexandru NICOLAU
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - Newer off-chip DRAM families, including Synchronous DRAMs (SDRAMs) and RAMBUS DRAMs (RDRAMs), are becoming standard choices for the design of high-performance systems. Although previous work in High-Level Synthesis (HLS) has addressed exploiting features of page-mode DRAMs, techniques do not exist for exploiting the two key features of these newer DRAM families that boost memory performance and help overcome bandwidth limitations: (1) burst mode access, and (2) interleaved access through multiple banks. We address pre-synthesis optimizations on the input behavior that extract and exploit the burst mode and multiple bank interleaved access modes of these newer DRAM families, so that these features can be exploited fully during the HLS trajectory. Our experiments, run on a suite of memory-intensive benchmarks using a contemporary SDRAM library, demonstrate significant performance improvements of up to 62.5% over the naive approach, and improvements of up to 16.7% over the previous approach that considered only page-mode or extended-data-out (EDO) DRAMS.
ER -