The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kenangan cache ialah salah satu faktor utama yang mempengaruhi prestasi perisian, dan penggunaannya menjadi semakin biasa walaupun dalam sistem terbenam. Analisis cekap kesan variasi parameter (saiz cache, tahap persekutuan, dasar penggantian, saiz talian, . . . ) pada masa yang sama merupakan aspek penting dan sangat memakan masa bagi reka bentuk sistem terbenam, yang kerumitannya meningkat apabila berbilang- tugasan dan aspek masa nyata mesti dipertimbangkan. Kami mencadangkan metodologi berasaskan simulasi baharu, memfokuskan pada model anggaran cache dan perisian reaktif berbilang tugas, yang membolehkan seseorang menukar dengan lancar antara ketepatan dan kelajuan simulasi. Khususnya, kami mencadangkan untuk mempertimbangkan konflik dalam tugas dengan tepat, tetapi menganggarkan konflik antara tugas dengan mempertimbangkan hanya sejumlah terhingga pelaksanaan tugas sebelumnya. Rasional untuk pilihan ini boleh didapati dalam corak biasa dalam sistem terbenam, di mana aliran data "normal" menghasilkan aliran biasa intra-tugas biasa, terganggu dari semasa ke semasa oleh beberapa peristiwa mendesak, yang secara pesimis boleh dianggap sebagai mengganggu. tingkah laku cache. Pendekatan ini adalah konservatif kerana pelaksanaan semula tugas selepas masa yang banyak akan sentiasa dianggap sebagai tiada dalam cache, dan kelajuan simulasi adalah agak besar.
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Salinan
Marcello LAJOLO, Luciano LAVAGNO, Alberto SANGIOVANNI-VINCENTELLI, "Fast Instruction Cache Simulation for Hardware/Software Co-Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2475-2484, November 1999, doi: .
Abstract: Cache memories are one of the main factors that affect software performance, and their use is becoming increasingly common even in embedded systems. Efficient analysis of the effects of parameter variations (cache size, degree of associativity, replacement policy, line size, . . . ) is at the same time an essential and very time-consuming aspect of embedded system design, whose complexity increases when multi-tasking and real-time aspects must be considered. We propose a new simulation-based methodology, focused on an approximate model of the cache and of the multi-tasking reactive software, that allows one to trade off smoothly between accuracy and simulation speed. In particular, we propose to accurately consider intra-task conflicts, but approximate inter-task conflicts by considering only a finite number of previous task executions. The rationale for this choice can be found in a common pattern in embedded systems, where a "normal" data flow results in a regular intra-task common flow, interrupted from time to time by some urgent event, that pessimistically can be considered as disrupting the cache behavior. The approach is conservative because re-execution of a task after a large amount of time will always be considered as not in cache, and the simulation speed-up is considerable.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2475/_p
Salinan
@ARTICLE{e82-a_11_2475,
author={Marcello LAJOLO, Luciano LAVAGNO, Alberto SANGIOVANNI-VINCENTELLI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Fast Instruction Cache Simulation for Hardware/Software Co-Design},
year={1999},
volume={E82-A},
number={11},
pages={2475-2484},
abstract={Cache memories are one of the main factors that affect software performance, and their use is becoming increasingly common even in embedded systems. Efficient analysis of the effects of parameter variations (cache size, degree of associativity, replacement policy, line size, . . . ) is at the same time an essential and very time-consuming aspect of embedded system design, whose complexity increases when multi-tasking and real-time aspects must be considered. We propose a new simulation-based methodology, focused on an approximate model of the cache and of the multi-tasking reactive software, that allows one to trade off smoothly between accuracy and simulation speed. In particular, we propose to accurately consider intra-task conflicts, but approximate inter-task conflicts by considering only a finite number of previous task executions. The rationale for this choice can be found in a common pattern in embedded systems, where a "normal" data flow results in a regular intra-task common flow, interrupted from time to time by some urgent event, that pessimistically can be considered as disrupting the cache behavior. The approach is conservative because re-execution of a task after a large amount of time will always be considered as not in cache, and the simulation speed-up is considerable.},
keywords={},
doi={},
ISSN={},
month={November},}
Salinan
TY - JOUR
TI - Fast Instruction Cache Simulation for Hardware/Software Co-Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2475
EP - 2484
AU - Marcello LAJOLO
AU - Luciano LAVAGNO
AU - Alberto SANGIOVANNI-VINCENTELLI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - Cache memories are one of the main factors that affect software performance, and their use is becoming increasingly common even in embedded systems. Efficient analysis of the effects of parameter variations (cache size, degree of associativity, replacement policy, line size, . . . ) is at the same time an essential and very time-consuming aspect of embedded system design, whose complexity increases when multi-tasking and real-time aspects must be considered. We propose a new simulation-based methodology, focused on an approximate model of the cache and of the multi-tasking reactive software, that allows one to trade off smoothly between accuracy and simulation speed. In particular, we propose to accurately consider intra-task conflicts, but approximate inter-task conflicts by considering only a finite number of previous task executions. The rationale for this choice can be found in a common pattern in embedded systems, where a "normal" data flow results in a regular intra-task common flow, interrupted from time to time by some urgent event, that pessimistically can be considered as disrupting the cache behavior. The approach is conservative because re-execution of a task after a large amount of time will always be considered as not in cache, and the simulation speed-up is considerable.
ER -