The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam kertas kerja ini, kami memperkenalkan Pengesan Frekuensi Fasa (PFD) berkelajuan tinggi dan berkuasa rendah yang direka bentuk menggunakan tepi positif TSPC (Jam Satu Fasa Sejati) yang diubah suai yang dicetuskan flip-flop D. PFD yang dicadangkan mempunyai struktur mudah dengan hanya menggunakan 19 transistor. Julat operasi PFD ini melebihi 1.4 GHz tanpa menggunakan litar praskala tambahan. Tambahan pula, PFD mempunyai zon mati kurang daripada 0.01ns dalam ciri fasa dan mempunyai ralat sensitiviti fasa rendah. Julat pengesanan ralat fasa dan kekerapan tidak terhad seperti dalam kes PFD jenis pt dan jenis nc. Selain itu, PFD adalah bebas daripada kitaran tugas isyarat input. Juga, litar pam cas baharu dipersembahkan berdasarkan penguat cas. Arus siap sedia bagi litar pam cas yang dicadangkan meningkatkan kelajuan pam cas dan mengeluarkan perkongsian cas yang menyebabkan bunyi fasa dalam pam cas PLL. Tambahan pula, kesan suapan jam dikurangkan dengan memisahkan peringkat output daripada isyarat atas dan bawah. Hasil simulasi berdasarkan PLL pesanan ketiga dibentangkan untuk mengesahkan proses penguncian dengan PFD dan litar pam cas yang dicadangkan. Litar PFD dan pam cas yang dicadangkan direka menggunakan teknologi CMOS 0.8 µm dengan voltan bekalan 5 V.
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Salinan
Won-Hyo LEE, Sung-Dae LEE, Jun-Dong CHO, "A High-Speed, Low-Power Phase Frequency Detector and Charge-Pump Circuits for High Frequency Phase-Locked Loops" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2514-2520, November 1999, doi: .
Abstract: In this paper, we introduce a high-speed and low-power Phase-Frequency Detector (PFD) that is designed using a modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop . The proposed PFD has a simple structure with using only 19 transistors. The operation range of this PFD is over 1.4 GHz without using additional prescaler circuits. Furthermore, the PFD has a dead zone less than 0.01ns in the phase characteristics and has low phase sensitivity errors. The phase and frequency error detection range is not limited as in the case of the pt-type and nc-type PFDs. Also, the PFD is independent of the duty cycle of input signals. Also, a new charge-pump circuit is presented that is based on a charge-amplifier. A stand-by current of the proposed charge-pump circuit enhances the speed of charge-pump and removes the charge sharing which causes a phase noise in the charge pump PLL. Furthermore, the effect of clock feedthrough is reduced by separating the output stage from up and down signal. The simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD and charge pump circuits. The proposed PFD and charge-pump circuits are designed using 0.8 µm CMOS technology with 5 V supply voltage.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2514/_p
Salinan
@ARTICLE{e82-a_11_2514,
author={Won-Hyo LEE, Sung-Dae LEE, Jun-Dong CHO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A High-Speed, Low-Power Phase Frequency Detector and Charge-Pump Circuits for High Frequency Phase-Locked Loops},
year={1999},
volume={E82-A},
number={11},
pages={2514-2520},
abstract={In this paper, we introduce a high-speed and low-power Phase-Frequency Detector (PFD) that is designed using a modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop . The proposed PFD has a simple structure with using only 19 transistors. The operation range of this PFD is over 1.4 GHz without using additional prescaler circuits. Furthermore, the PFD has a dead zone less than 0.01ns in the phase characteristics and has low phase sensitivity errors. The phase and frequency error detection range is not limited as in the case of the pt-type and nc-type PFDs. Also, the PFD is independent of the duty cycle of input signals. Also, a new charge-pump circuit is presented that is based on a charge-amplifier. A stand-by current of the proposed charge-pump circuit enhances the speed of charge-pump and removes the charge sharing which causes a phase noise in the charge pump PLL. Furthermore, the effect of clock feedthrough is reduced by separating the output stage from up and down signal. The simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD and charge pump circuits. The proposed PFD and charge-pump circuits are designed using 0.8 µm CMOS technology with 5 V supply voltage. },
keywords={},
doi={},
ISSN={},
month={November},}
Salinan
TY - JOUR
TI - A High-Speed, Low-Power Phase Frequency Detector and Charge-Pump Circuits for High Frequency Phase-Locked Loops
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2514
EP - 2520
AU - Won-Hyo LEE
AU - Sung-Dae LEE
AU - Jun-Dong CHO
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - In this paper, we introduce a high-speed and low-power Phase-Frequency Detector (PFD) that is designed using a modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop . The proposed PFD has a simple structure with using only 19 transistors. The operation range of this PFD is over 1.4 GHz without using additional prescaler circuits. Furthermore, the PFD has a dead zone less than 0.01ns in the phase characteristics and has low phase sensitivity errors. The phase and frequency error detection range is not limited as in the case of the pt-type and nc-type PFDs. Also, the PFD is independent of the duty cycle of input signals. Also, a new charge-pump circuit is presented that is based on a charge-amplifier. A stand-by current of the proposed charge-pump circuit enhances the speed of charge-pump and removes the charge sharing which causes a phase noise in the charge pump PLL. Furthermore, the effect of clock feedthrough is reduced by separating the output stage from up and down signal. The simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD and charge pump circuits. The proposed PFD and charge-pump circuits are designed using 0.8 µm CMOS technology with 5 V supply voltage.
ER -