The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Makalah ini mencadangkan pengganda analog CMOS novel. Sebagai merit pentingnya, ia bebas daripada pengurangan mobiliti dan kesan badan. Oleh itu, pengganda yang dicadangkan dijangka mempunyai kelinearan yang baik, berbanding dengan pengganda konvensional. Empat transistor yang beroperasi di kawasan linear membentuk sel input bagi pengganda. Sumber dan pintu belakang mereka disambungkan ke tanah untuk membatalkan kesan badan. ePintu mereka dipasang pada voltan pincang yang sama untuk menghilangkan kesan pengurangan mobiliti. Isyarat input digunakan pada longkang transistor sel input melalui nullors diubah suai. Keputusan simulasi menunjukkan bahawa THD adalah kurang daripada 0.8% untuk 0.6 V hlm isyarat input pada voltan bekalan 2.5-V, dan lebar jalur 3-dB adalah sehingga kira-kira 13.3 MHz.
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Salinan
Eitake IBARAGI, Akira HYOGO, Keitaro SEKINE, "A CMOS Analog Multiplier Free from Mobility Reduction and Body Effect" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 2, pp. 327-334, February 1999, doi: .
Abstract: This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. eTheir gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V p-p input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_2_327/_p
Salinan
@ARTICLE{e82-a_2_327,
author={Eitake IBARAGI, Akira HYOGO, Keitaro SEKINE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A CMOS Analog Multiplier Free from Mobility Reduction and Body Effect},
year={1999},
volume={E82-A},
number={2},
pages={327-334},
abstract={This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. eTheir gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V p-p input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.},
keywords={},
doi={},
ISSN={},
month={February},}
Salinan
TY - JOUR
TI - A CMOS Analog Multiplier Free from Mobility Reduction and Body Effect
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 327
EP - 334
AU - Eitake IBARAGI
AU - Akira HYOGO
AU - Keitaro SEKINE
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1999
AB - This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. eTheir gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V p-p input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.
ER -