The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini membentangkan litar saraf menggunakan teknik PWM berdasarkan seni bina litar gabungan analog-digital. Beberapa teknik litar PWM baharu dicadangkan. Litar penjumlahan berwajaran bipolar diterangkan yang mencapai ketepatan 8-bit dalam simulasi SPICE pada voltan bekalan 5 V dengan mengimbangi kesan kemuatan parasit. Pembanding selak jenis pembezaan prestasi tinggi yang boleh mendiskriminasi perbezaan 1 mV pada 100 MHz dalam simulasi SPICE juga diterangkan. Seterusnya, kami membentangkan cip prototaip yang direka menggunakan proses CMOS 0.6µm. Keputusan pengukuran menunjukkan bahawa ketepatan keseluruhan dalam penjumlahan berwajaran dan transformasi sigmoid ialah 5 bit. Rangkaian saraf telah dibina menggunakan cip prototaip, dan keputusan eksperimen untuk merealisasikan fungsi XOR telah berjaya mengesahkan operasi saraf asas.
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Salinan
Takashi MORIE, Jun FUNAKOSHI, Makoto NAGATA, Atsushi IWATA, "An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 2, pp. 356-363, February 1999, doi: .
Abstract: This paper presents a neural circuit using PWM technique based on an analog-digital merged circuit architecture. Some new PWM circuit techniques are proposed. A bipolar-weighted summation circuit is described which attains 8-bit precision in SPICE simulation at 5 V supply voltage by compensating parasitic capacitance effects. A high performance differential-type latch comparator which can discriminate 1 mV difference at 100 MHz in SPICE simulation is also described. Next, we present a prototype chip fabricated using a 0.6µm CMOS process. The measurement results demonstrate that the overall precision in the weighted summation and the sigmoidal transformation is 5 bits. A neural network has been constructed using the prototype chips, and the experimental results for realizing the XOR function have successfully verified the basic neural operation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_2_356/_p
Salinan
@ARTICLE{e82-a_2_356,
author={Takashi MORIE, Jun FUNAKOSHI, Makoto NAGATA, Atsushi IWATA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique},
year={1999},
volume={E82-A},
number={2},
pages={356-363},
abstract={This paper presents a neural circuit using PWM technique based on an analog-digital merged circuit architecture. Some new PWM circuit techniques are proposed. A bipolar-weighted summation circuit is described which attains 8-bit precision in SPICE simulation at 5 V supply voltage by compensating parasitic capacitance effects. A high performance differential-type latch comparator which can discriminate 1 mV difference at 100 MHz in SPICE simulation is also described. Next, we present a prototype chip fabricated using a 0.6µm CMOS process. The measurement results demonstrate that the overall precision in the weighted summation and the sigmoidal transformation is 5 bits. A neural network has been constructed using the prototype chips, and the experimental results for realizing the XOR function have successfully verified the basic neural operation.},
keywords={},
doi={},
ISSN={},
month={February},}
Salinan
TY - JOUR
TI - An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 356
EP - 363
AU - Takashi MORIE
AU - Jun FUNAKOSHI
AU - Makoto NAGATA
AU - Atsushi IWATA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1999
AB - This paper presents a neural circuit using PWM technique based on an analog-digital merged circuit architecture. Some new PWM circuit techniques are proposed. A bipolar-weighted summation circuit is described which attains 8-bit precision in SPICE simulation at 5 V supply voltage by compensating parasitic capacitance effects. A high performance differential-type latch comparator which can discriminate 1 mV difference at 100 MHz in SPICE simulation is also described. Next, we present a prototype chip fabricated using a 0.6µm CMOS process. The measurement results demonstrate that the overall precision in the weighted summation and the sigmoidal transformation is 5 bits. A neural network has been constructed using the prototype chips, and the experimental results for realizing the XOR function have successfully verified the basic neural operation.
ER -