The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Transistor komposit CMOS berkelajuan tinggi voltan rendah baharu dipersembahkan. Ia menurunkan voltan bekalan ke |Vt|+2 Vds, duduk dan dengan ketara memanjangkan julat pengendalian voltan input dan mencapai operasi berkelajuan tinggi. Sebagai contoh aplikasi, ia digunakan dalam reka bentuk pengganda analog empat kuadran berkelajuan tinggi. Hasil simulasi menggunakan proses telaga 2µm MOSIS dengan bekalan 3 V diberikan.
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Salinan
Changku HWANG, Akira HYOGO, Hong-sun KIM, Mohammed ISMAIL, Keitaro SEKINE, "Low Voltage High-Speed CMOS Square-Law Composite Transistor Cell" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 2, pp. 378-379, February 1999, doi: .
Abstract: A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |Vt|+2 Vds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2µm N-well process with a 3 V supply are given.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_2_378/_p
Salinan
@ARTICLE{e82-a_2_378,
author={Changku HWANG, Akira HYOGO, Hong-sun KIM, Mohammed ISMAIL, Keitaro SEKINE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low Voltage High-Speed CMOS Square-Law Composite Transistor Cell},
year={1999},
volume={E82-A},
number={2},
pages={378-379},
abstract={A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |Vt|+2 Vds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2µm N-well process with a 3 V supply are given.},
keywords={},
doi={},
ISSN={},
month={February},}
Salinan
TY - JOUR
TI - Low Voltage High-Speed CMOS Square-Law Composite Transistor Cell
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 378
EP - 379
AU - Changku HWANG
AU - Akira HYOGO
AU - Hong-sun KIM
AU - Mohammed ISMAIL
AU - Keitaro SEKINE
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1999
AB - A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |Vt|+2 Vds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2µm N-well process with a 3 V supply are given.
ER -