The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Masa penguncian pensintesis frekuensi PLL bergantung terutamanya pada jumlah perolehan gelung. Oleh kerana keuntungan pengesan fasa konvensional adalah malar, adalah sukar untuk memperbaiki masa penguncian oleh pengesan fasa. Dalam makalah ini, kami mempertimbangkan semula operasi pengesan fasa dan mencadangkan pensintesis frekuensi PLL dengan pengesan berbilang fasa di mana keuntungan pengesan fasa ditingkatkan dengan menggunakan pengesan fasa empat peringkat dan pam cas. Kemudian, masa penguncian kelajuan yang lebih tinggi dan ciri-ciri palsu yang baik boleh dicapai.
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Salinan
Yasuaki SUMI, Kouichi SYOUBU, Shigeki OBOTE, Yutaka FUKUI, Yoshio ITOH, "PLL Frequency Synthesizer with Multi-Phase Detector" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 3, pp. 431-435, March 1999, doi: .
Abstract: The lock-up time of a PLL frequency synthesizer mainly depends on the total loop gain. Since the gain of the conventional phase detector is constant, it is difficult to improve the lock-up time by the phase detector. In this paper, we reconsider the operation of the phase detector and propose the PLL frequency synthesizer with multi-phase detector in which the gain of phase detector is increased by using four stage phase detectors and charge pumps. Then, a higher speed lock-up time and good spurious characteristics can be achieved.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_3_431/_p
Salinan
@ARTICLE{e82-a_3_431,
author={Yasuaki SUMI, Kouichi SYOUBU, Shigeki OBOTE, Yutaka FUKUI, Yoshio ITOH, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={PLL Frequency Synthesizer with Multi-Phase Detector},
year={1999},
volume={E82-A},
number={3},
pages={431-435},
abstract={The lock-up time of a PLL frequency synthesizer mainly depends on the total loop gain. Since the gain of the conventional phase detector is constant, it is difficult to improve the lock-up time by the phase detector. In this paper, we reconsider the operation of the phase detector and propose the PLL frequency synthesizer with multi-phase detector in which the gain of phase detector is increased by using four stage phase detectors and charge pumps. Then, a higher speed lock-up time and good spurious characteristics can be achieved.},
keywords={},
doi={},
ISSN={},
month={March},}
Salinan
TY - JOUR
TI - PLL Frequency Synthesizer with Multi-Phase Detector
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 431
EP - 435
AU - Yasuaki SUMI
AU - Kouichi SYOUBU
AU - Shigeki OBOTE
AU - Yutaka FUKUI
AU - Yoshio ITOH
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1999
AB - The lock-up time of a PLL frequency synthesizer mainly depends on the total loop gain. Since the gain of the conventional phase detector is constant, it is difficult to improve the lock-up time by the phase detector. In this paper, we reconsider the operation of the phase detector and propose the PLL frequency synthesizer with multi-phase detector in which the gain of phase detector is increased by using four stage phase detectors and charge pumps. Then, a higher speed lock-up time and good spurious characteristics can be achieved.
ER -