The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Memandangkan fungsi sistem semakin kompleks, penggunaan semula IP (Harta Intelektual) adalah trend gaya reka bentuk sistem. Pereka bentuk perlu menilai prestasi dan ciri setiap blok IP calon yang boleh digunakan dalam reka bentuk mereka, manakala pembekal IP berharap untuk merahsiakan struktur blok IP mereka. Model kuasa tahap IP ialah model yang hanya mengambil statistik input utama sebagai parameter dan tidak mendedahkan sebarang maklumat tentang saiz transistor atau struktur litar. Kertas ini mencadangkan kaedah baharu untuk membina model kuasa yang sesuai untuk blok litar peringkat IP. Ia adalah kaedah pemilihan titik nominal untuk model kuasa berdasarkan sensitiviti kuasa. Dengan menganalisis hubungan antara penggunaan kuasa dinamik litar CMOS dan statistik isyarat inputnya, garis panduan memilih titik nominal dicadangkan. Daripada analisis kami, titik nominal pertama dipilih untuk meminimumkan ralat anggaran purata dan dua titik nominal lain dipilih untuk meminimumkan ralat anggaran maksimum. Keputusan eksperimen kami pada beberapa litar penanda aras menunjukkan keberkesanan kaedah yang dicadangkan. Purata ketepatan anggaran dalam 5.78% daripada simulasi tahap transistor dicapai. Kaedah yang dicadangkan boleh digunakan untuk membina persekitaran anggaran kuasa tahap sistem tanpa mendedahkan kandungan blok IP di dalamnya. Oleh itu, ia adalah kaedah yang menjanjikan untuk pembinaan model kuasa tahap IP.
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Salinan
Heng-Liang HUANG, Jiing-Yuan LIN, Wen-Zen SHEN, Jing-Yang JOU, "A New Method for Constructing IP Level Power Model Based on Power Sensitivity" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2431-2438, December 2000, doi: .
Abstract: As the function of a system getting more complex, IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of their IP blocks a secret. An IP level power model is a model that takes only the primary input statistics as parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method for power models based on power sensitivities. By analyzing the relationship between the dynamic power consumption of CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis, the first nominal point is selected to minimize the average estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can be applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby, it is a promising method for IP level power model construction.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2431/_p
Salinan
@ARTICLE{e83-a_12_2431,
author={Heng-Liang HUANG, Jiing-Yuan LIN, Wen-Zen SHEN, Jing-Yang JOU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A New Method for Constructing IP Level Power Model Based on Power Sensitivity},
year={2000},
volume={E83-A},
number={12},
pages={2431-2438},
abstract={As the function of a system getting more complex, IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of their IP blocks a secret. An IP level power model is a model that takes only the primary input statistics as parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method for power models based on power sensitivities. By analyzing the relationship between the dynamic power consumption of CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis, the first nominal point is selected to minimize the average estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can be applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby, it is a promising method for IP level power model construction.},
keywords={},
doi={},
ISSN={},
month={December},}
Salinan
TY - JOUR
TI - A New Method for Constructing IP Level Power Model Based on Power Sensitivity
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2431
EP - 2438
AU - Heng-Liang HUANG
AU - Jiing-Yuan LIN
AU - Wen-Zen SHEN
AU - Jing-Yang JOU
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - As the function of a system getting more complex, IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of their IP blocks a secret. An IP level power model is a model that takes only the primary input statistics as parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method for power models based on power sensitivities. By analyzing the relationship between the dynamic power consumption of CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis, the first nominal point is selected to minimize the average estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can be applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby, it is a promising method for IP level power model construction.
ER -