The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Penukar A/D stereo (ADC) 24-bit, 96 kHz untuk audio DVD telah dibangunkan. Cip tunggal menyepadukan modulator delta-sigma stereo (Δ ΣM's), rujukan voltan, dan penapis penyusutan. Δ ΣM tertib keempat menggunakan teknik maklum balas tempatan digunakan untuk mengelakkan beban berlebihan tanpa mengorbankan prestasi bunyi. Teknik suis-kapasitor kuasa rendah telah digunakan untuk pelaksanaan. Seni bina penapis pereputan dua peringkat yang mengurangkan bunyi pensuisan digital turut dibangunkan. Penapis sikat berbilang peringkat yang digabungkan telah digunakan untuk peringkat pertama, dan penapis tindak balas impuls terhingga (FIR) bersiri bit digunakan untuk peringkat kedua. 18.0 mm2 cip telah direka dalam CMOS 0.6-µm dengan peranti ambang rendah. Keputusan yang diukur menunjukkan julat dinamik berwajaran A 117 dB dalam jalur laluan 20 kHz, dengan pelesapan kuasa 470 mW pada operasi 5 V.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Salinan
Ichiro FUJIMORI, "A Single-Chip Stereo Audio Delta-Sigma A/D Converter with 117 dB Dynamic Range" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 2, pp. 243-251, February 2000, doi: .
Abstract: A 24-bit, 96 kHz stereo A/D converter (ADC) for DVD-audio has been developed. The single-chip integrates stereo delta-sigma modulators (Δ ΣM's), a voltage reference, and a decimation filter. A fourth-order cascaded Δ ΣM using a local feedback technique was employed to avoid overload without sacrificing noise performance. Low power switched-capacitor techniques were used for implementation. A two-stage decimation filter architecture that reduces digital switching noise was also developed. A merged multi-stage comb filter was used for the first stage, and a bit-serial finite-impulse-response (FIR) filter was used for the second stage. The 18.0 mm2 chip was fabricated in 0.6-µm CMOS with low threshold devices. Measured results show 117 dB A-weighted dynamic range in the 20 kHz passband, with 470 mW power dissipation at 5 V operation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_2_243/_p
Salinan
@ARTICLE{e83-a_2_243,
author={Ichiro FUJIMORI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Single-Chip Stereo Audio Delta-Sigma A/D Converter with 117 dB Dynamic Range},
year={2000},
volume={E83-A},
number={2},
pages={243-251},
abstract={A 24-bit, 96 kHz stereo A/D converter (ADC) for DVD-audio has been developed. The single-chip integrates stereo delta-sigma modulators (Δ ΣM's), a voltage reference, and a decimation filter. A fourth-order cascaded Δ ΣM using a local feedback technique was employed to avoid overload without sacrificing noise performance. Low power switched-capacitor techniques were used for implementation. A two-stage decimation filter architecture that reduces digital switching noise was also developed. A merged multi-stage comb filter was used for the first stage, and a bit-serial finite-impulse-response (FIR) filter was used for the second stage. The 18.0 mm2 chip was fabricated in 0.6-µm CMOS with low threshold devices. Measured results show 117 dB A-weighted dynamic range in the 20 kHz passband, with 470 mW power dissipation at 5 V operation.},
keywords={},
doi={},
ISSN={},
month={February},}
Salinan
TY - JOUR
TI - A Single-Chip Stereo Audio Delta-Sigma A/D Converter with 117 dB Dynamic Range
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 243
EP - 251
AU - Ichiro FUJIMORI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2000
AB - A 24-bit, 96 kHz stereo A/D converter (ADC) for DVD-audio has been developed. The single-chip integrates stereo delta-sigma modulators (Δ ΣM's), a voltage reference, and a decimation filter. A fourth-order cascaded Δ ΣM using a local feedback technique was employed to avoid overload without sacrificing noise performance. Low power switched-capacitor techniques were used for implementation. A two-stage decimation filter architecture that reduces digital switching noise was also developed. A merged multi-stage comb filter was used for the first stage, and a bit-serial finite-impulse-response (FIR) filter was used for the second stage. The 18.0 mm2 chip was fabricated in 0.6-µm CMOS with low threshold devices. Measured results show 117 dB A-weighted dynamic range in the 20 kHz passband, with 470 mW power dissipation at 5 V operation.
ER -