The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam pensintesis frekuensi gelung berkunci fasa (PLL) dengan perbandingan fasa perduaan, jitter sukar ditekan. Dalam kertas ini, kami mencadangkan pensintesis frekuensi PLL dengan perbandingan fasa binari yang lebih baik yang boleh menyelesaikan masalah di atas. Keberkesanan kaedah yang dicadangkan disahkan oleh keputusan simulasi PSpice.
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Salinan
Shigeki OBOTE, Yasuaki SUMI, Naoki KITAI, Yutaka FUKUI, Yoshio ITOH, "PLL Frequency Synthesizer with Binary Phase Comparison" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 3, pp. 427-434, March 2000, doi: .
Abstract: In a phase-locked-loop (PLL) frequency synthesizer with binary phase comparison, jitter is hard to suppress. In this paper, we propose a PLL frequency synthesizer with an improved binary phase comparison which can solve the above problem. The effectiveness of the proposed method is confirmed by PSpice simulation results.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_3_427/_p
Salinan
@ARTICLE{e83-a_3_427,
author={Shigeki OBOTE, Yasuaki SUMI, Naoki KITAI, Yutaka FUKUI, Yoshio ITOH, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={PLL Frequency Synthesizer with Binary Phase Comparison},
year={2000},
volume={E83-A},
number={3},
pages={427-434},
abstract={In a phase-locked-loop (PLL) frequency synthesizer with binary phase comparison, jitter is hard to suppress. In this paper, we propose a PLL frequency synthesizer with an improved binary phase comparison which can solve the above problem. The effectiveness of the proposed method is confirmed by PSpice simulation results.},
keywords={},
doi={},
ISSN={},
month={March},}
Salinan
TY - JOUR
TI - PLL Frequency Synthesizer with Binary Phase Comparison
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 427
EP - 434
AU - Shigeki OBOTE
AU - Yasuaki SUMI
AU - Naoki KITAI
AU - Yutaka FUKUI
AU - Yoshio ITOH
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2000
AB - In a phase-locked-loop (PLL) frequency synthesizer with binary phase comparison, jitter is hard to suppress. In this paper, we propose a PLL frequency synthesizer with an improved binary phase comparison which can solve the above problem. The effectiveness of the proposed method is confirmed by PSpice simulation results.
ER -