The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Makalah ini menerangkan litar pemulihan data pensampelan berlebihan yang terdiri daripada gelung terkunci kelewatan analog dan logik keputusan digital. Teknik pensampelan berlebihan novel adalah berdasarkan litar gelung terkunci kelewatan yang dikunci kepada berbilang tempoh jam dan bukannya tempoh jam tunggal, yang menjana resolusi pemasaan kurang daripada kelewatan gerbang rantaian kelewatan. Logik digital untuk pemulihan data telah dilaksanakan dengan andaian bahawa tiada sisihan frekuensi yang menjejaskan pusat data yang diperoleh. Cip telah direka menggunakan teknologi CMOS 0.6 µm. Cip telah diuji pada data input NRZ 1.0 Gb/s dengan jam 125 MHz dan memulihkan data input bersiri ke dalam lapan aliran keluaran 125 Mb/s.
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Salinan
Jun-Young PARK, Jin-Ku KANG, "A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 6, pp. 1100-1105, June 2000, doi: .
Abstract: This paper describes an oversampling data recovery circuit composed of an analog delay locked loop and a digital decision logic. The novel oversampling technique is based on the delay locked loop circuit locked to multiple clock periods rather than a single clock period, which generates the timing resolution less than the gate delay of the delay chain. The digital logic for data recovery was implemented with the assumption that there is no frequency deviation that hurts the center of acquired data. The chip has been fabricated using 0.6 µm CMOS technology. The chip has been tested at 1.0 Gb/s NRZ input data with 125 MHz clock and recovers the serial input data into eight 125 Mb/s output stream.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_6_1100/_p
Salinan
@ARTICLE{e83-a_6_1100,
author={Jun-Young PARK, Jin-Ku KANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method},
year={2000},
volume={E83-A},
number={6},
pages={1100-1105},
abstract={This paper describes an oversampling data recovery circuit composed of an analog delay locked loop and a digital decision logic. The novel oversampling technique is based on the delay locked loop circuit locked to multiple clock periods rather than a single clock period, which generates the timing resolution less than the gate delay of the delay chain. The digital logic for data recovery was implemented with the assumption that there is no frequency deviation that hurts the center of acquired data. The chip has been fabricated using 0.6 µm CMOS technology. The chip has been tested at 1.0 Gb/s NRZ input data with 125 MHz clock and recovers the serial input data into eight 125 Mb/s output stream.},
keywords={},
doi={},
ISSN={},
month={June},}
Salinan
TY - JOUR
TI - A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1100
EP - 1105
AU - Jun-Young PARK
AU - Jin-Ku KANG
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2000
AB - This paper describes an oversampling data recovery circuit composed of an analog delay locked loop and a digital decision logic. The novel oversampling technique is based on the delay locked loop circuit locked to multiple clock periods rather than a single clock period, which generates the timing resolution less than the gate delay of the delay chain. The digital logic for data recovery was implemented with the assumption that there is no frequency deviation that hurts the center of acquired data. The chip has been fabricated using 0.6 µm CMOS technology. The chip has been tested at 1.0 Gb/s NRZ input data with 125 MHz clock and recovers the serial input data into eight 125 Mb/s output stream.
ER -