The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Makalah ini membentangkan algoritma pemetaan teknologi CAD untuk FPGA berasaskan LUT. Memandangkan interkoneksi dalam FPGA mesti dicapai dengan sumber penghalaan yang terhad, kebolehhalaan adalah objektif paling penting dalam algoritma pemetaan teknologi. Untuk mengoptimumkan kebolehhalaan, matlamat algoritma ialah penghasilan reka bentuk dengan sambungan minimum. Algoritma Min-cut pertama kali digunakan untuk membahagikan graf yang mewakili rangkaian Boolean ke dalam kelompok supaya jumlah bilangan interkoneksi antara kelompok adalah minimum. Untuk mengurangkan lagi bilangan interkoneksi yang diperlukan, kluster kemudiannya digabungkan menjadi kluster yang lebih besar melalui teknik berpasangan. Algoritma ini telah diuji pada litar penanda aras MCNC. Berbanding dengan algoritma pemetaan FPGA berasaskan LUT yang lain, algoritma menghasilkan ciri kebolehhalaan yang lebih baik.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Salinan
Chi-Chou KAO, Yen-Tai LAI, "A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2690-2696, November 2001, doi: .
Abstract: This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnections needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2690/_p
Salinan
@ARTICLE{e84-a_11_2690,
author={Chi-Chou KAO, Yen-Tai LAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs},
year={2001},
volume={E84-A},
number={11},
pages={2690-2696},
abstract={This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnections needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.},
keywords={},
doi={},
ISSN={},
month={November},}
Salinan
TY - JOUR
TI - A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2690
EP - 2696
AU - Chi-Chou KAO
AU - Yen-Tai LAI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnections needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.
ER -