The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kekangan Sempadan Pelan lantai VLSI memerlukan satu set blok untuk diletakkan di sepanjang sempadan cip. Oleh itu, set blok ini boleh bersebelahan dengan pad I/O untuk komunikasi luaran. Tambahan pula, blok ini dijauhkan dari kawasan tengah supaya ia tidak membentuk sekatan untuk laluan dalaman. Dalam kertas kerja, kami merangka algoritma perancangan lantai VLSI dengan kekangan sempadan menggunakan perwakilan Senarai Blok Sudut (CBL). Kami mengenal pasti syarat yang perlu dan mencukupi bagi perwakilan CBL untuk kekangan sempadan. Kami mereka bentuk pendekatan masa linear untuk mengimbas keadaan dan merumuskan fungsi penalti untuk menghukum pelanggaran kekangan. Proses penyepuhlindapan simulasi diguna pakai untuk mengoptimumkan pelan lantai. Eksperimen pada penanda aras MCNC menunjukkan hasil yang menjanjikan.
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Salinan
Yuchun MA, Xianlong HONG, Sheqin DONG, Yici CAI, Chung-Kuan CHENG, Jun GU, "VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2697-2704, November 2001, doi: .
Abstract: Boundary Constraints of VLSI floorplanning require a set of blocks to be placed along the boundaries of the chip. Thus, this set of blocks can be adjacent to I/O pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for internal routing. In the paper, we devise an algorithm of VLSI floorplanning with boundary constraints using a Corner Block List (CBL) representation. We identify the necessary and sufficient conditions of the CBL representation for the boundary constraints. We design a linear time approach to scan the conditions and formulate a penalty function to punish the constraint violation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2697/_p
Salinan
@ARTICLE{e84-a_11_2697,
author={Yuchun MA, Xianlong HONG, Sheqin DONG, Yici CAI, Chung-Kuan CHENG, Jun GU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation},
year={2001},
volume={E84-A},
number={11},
pages={2697-2704},
abstract={Boundary Constraints of VLSI floorplanning require a set of blocks to be placed along the boundaries of the chip. Thus, this set of blocks can be adjacent to I/O pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for internal routing. In the paper, we devise an algorithm of VLSI floorplanning with boundary constraints using a Corner Block List (CBL) representation. We identify the necessary and sufficient conditions of the CBL representation for the boundary constraints. We design a linear time approach to scan the conditions and formulate a penalty function to punish the constraint violation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.},
keywords={},
doi={},
ISSN={},
month={November},}
Salinan
TY - JOUR
TI - VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2697
EP - 2704
AU - Yuchun MA
AU - Xianlong HONG
AU - Sheqin DONG
AU - Yici CAI
AU - Chung-Kuan CHENG
AU - Jun GU
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - Boundary Constraints of VLSI floorplanning require a set of blocks to be placed along the boundaries of the chip. Thus, this set of blocks can be adjacent to I/O pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for internal routing. In the paper, we devise an algorithm of VLSI floorplanning with boundary constraints using a Corner Block List (CBL) representation. We identify the necessary and sufficient conditions of the CBL representation for the boundary constraints. We design a linear time approach to scan the conditions and formulate a penalty function to punish the constraint violation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.
ER -