The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam kertas ini, kami mencadangkan kaedah sintesis pokok jam baharu untuk litar separa segerak. Pokok jam yang diperolehi melalui kaedah yang dicadangkan ialah pokok jam pelbagai arah berbilang peringkat supaya pemasaan input jam bagi setiap daftar ialah gandaan kelewatan unit yang dipratentukan dan panjang wayar daripada penimbal jam kepada elemen yang didorong olehnya. adalah bersempadan. Pokok jam dibina untuk beberapa litar praktikal. Saiz pokok jam yang dibina adalah setanding dengan pokok jam condong sifar. Untuk memastikan kualiti praktikal pokok jam, ia diperiksa di bawah lima keadaan kelewatan, yang meliputi pelbagai keadaan persekitaran dan pembuatan. Hasilnya, mereka terbukti stabil di bawah setiap keadaan dan meningkatkan kelajuan jam sehingga 17.3% berbanding pokok jam condong sifar.
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Salinan
Keiichi KUROKAWA, Takuya YASUI, Masahiko TOYONAGA, Atsushi TAKAHASHI, "A Practical Clock Tree Synthesis for Semi-Synchronous Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2705-2713, November 2001, doi: .
Abstract: In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such that a clock-input timing of each register is a multiple of a predefined unit delay and the wire length from a clock buffer to an element driven by it is bounded. The clock trees are constructed for several practical circuits. The size of constructed clock tree is comparable to a zero skew clock tree. In order to assure the practical quality of the clock trees, they are examined under the five delay conditions, which cover various environmental and manufacturing conditions. As a result, they are proved stable under each condition and improve the clock speed up to 17.3% against the zero skew clock trees.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2705/_p
Salinan
@ARTICLE{e84-a_11_2705,
author={Keiichi KUROKAWA, Takuya YASUI, Masahiko TOYONAGA, Atsushi TAKAHASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Practical Clock Tree Synthesis for Semi-Synchronous Circuits},
year={2001},
volume={E84-A},
number={11},
pages={2705-2713},
abstract={In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such that a clock-input timing of each register is a multiple of a predefined unit delay and the wire length from a clock buffer to an element driven by it is bounded. The clock trees are constructed for several practical circuits. The size of constructed clock tree is comparable to a zero skew clock tree. In order to assure the practical quality of the clock trees, they are examined under the five delay conditions, which cover various environmental and manufacturing conditions. As a result, they are proved stable under each condition and improve the clock speed up to 17.3% against the zero skew clock trees.},
keywords={},
doi={},
ISSN={},
month={November},}
Salinan
TY - JOUR
TI - A Practical Clock Tree Synthesis for Semi-Synchronous Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2705
EP - 2713
AU - Keiichi KUROKAWA
AU - Takuya YASUI
AU - Masahiko TOYONAGA
AU - Atsushi TAKAHASHI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such that a clock-input timing of each register is a multiple of a predefined unit delay and the wire length from a clock buffer to an element driven by it is bounded. The clock trees are constructed for several practical circuits. The size of constructed clock tree is comparable to a zero skew clock tree. In order to assure the practical quality of the clock trees, they are examined under the five delay conditions, which cover various environmental and manufacturing conditions. As a result, they are proved stable under each condition and improve the clock speed up to 17.3% against the zero skew clock trees.
ER -