The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Oleh kerana LSI ialah struktur dua dimensi, bilangan pin luaran meningkat pada kadar yang lebih rendah daripada peningkatan yang sepadan dalam bilangan get pada LSI. Oleh itu, bilangan flip-flop pada laluan imbasan meningkat apabila ketumpatan get pada LSI meningkat, menyebabkan masa penggunaan ujian lebih lama. Dalam makalah ini, tiga strategi DFT novel yang bertujuan untuk mengurangkan masa permohonan ujian dicadangkan. Strategi DFT 1 ialah kaedah reka bentuk imbasan penuh dengan sisipan titik ujian, strategi DFT 2 ialah kaedah reka bentuk imbasan separa, dan strategi DFT 3 ialah kaedah reka bentuk imbasan separa dengan sisipan titik ujian. Keputusan eksperimen menunjukkan bahawa strategi DFT ini mengurangkan masa permohonan ujian sebanyak 45% hingga 82% berbanding kaedah reka bentuk imbasan penuh konvensional.
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Salinan
Toshinori HOSOKAWA, Masayoshi YOSHIMURA, Mitsuyasu OHTA, "Novel DFT Strategies Using Full/Partial Scan Designs and Test Point Insertion to Reduce Test Application Time" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2722-2730, November 2001, doi: .
Abstract: As LSIs are two-dimensional structures, the number of external pins increases at a lower rate than the corresponding increase in the number of gates on the LSI. Therefore, the number of flip-flops on a scan path increases as the density of gates on LSIs rises, resulting in longer test application times. In this paper, three novel DFT strategies aimed at reducing test application time are proposed. DFT strategy 1 is a full scan design method with test point insertion, DFT strategy 2 is a partial scan design method, and DFT strategy 3 is a partial scan design method with test point insertion. Experimental results show that these DFT strategies reduced the test application times by 45% to 82% compared with conventional full scan design methods.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2722/_p
Salinan
@ARTICLE{e84-a_11_2722,
author={Toshinori HOSOKAWA, Masayoshi YOSHIMURA, Mitsuyasu OHTA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Novel DFT Strategies Using Full/Partial Scan Designs and Test Point Insertion to Reduce Test Application Time},
year={2001},
volume={E84-A},
number={11},
pages={2722-2730},
abstract={As LSIs are two-dimensional structures, the number of external pins increases at a lower rate than the corresponding increase in the number of gates on the LSI. Therefore, the number of flip-flops on a scan path increases as the density of gates on LSIs rises, resulting in longer test application times. In this paper, three novel DFT strategies aimed at reducing test application time are proposed. DFT strategy 1 is a full scan design method with test point insertion, DFT strategy 2 is a partial scan design method, and DFT strategy 3 is a partial scan design method with test point insertion. Experimental results show that these DFT strategies reduced the test application times by 45% to 82% compared with conventional full scan design methods.},
keywords={},
doi={},
ISSN={},
month={November},}
Salinan
TY - JOUR
TI - Novel DFT Strategies Using Full/Partial Scan Designs and Test Point Insertion to Reduce Test Application Time
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2722
EP - 2730
AU - Toshinori HOSOKAWA
AU - Masayoshi YOSHIMURA
AU - Mitsuyasu OHTA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - As LSIs are two-dimensional structures, the number of external pins increases at a lower rate than the corresponding increase in the number of gates on the LSI. Therefore, the number of flip-flops on a scan path increases as the density of gates on LSIs rises, resulting in longer test application times. In this paper, three novel DFT strategies aimed at reducing test application time are proposed. DFT strategy 1 is a full scan design method with test point insertion, DFT strategy 2 is a partial scan design method, and DFT strategy 3 is a partial scan design method with test point insertion. Experimental results show that these DFT strategies reduced the test application times by 45% to 82% compared with conventional full scan design methods.
ER -