The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Pin luaran untuk ujian adalah sumber perkakasan yang berharga kerana nombor ini sangat terhad. Teras diuji melalui mekanisme akses ujian (TAM) seperti seni bina bas ujian. Apabila teras diuji melalui bas ujian yang mempunyai lebar bit yang tetap, rangsangan ujian dan tindak balas ujian untuk teras tertentu perlu diangkut melalui bas ujian ini. Teras mungkin memerlukan lebih lebar untuk input dan output daripada bas ujian, dan oleh itu, untuk beberapa bahagian ujian, TAM adalah melahu; ini adalah penggunaan TAM yang membazir. Dalam makalah ini, kaedah pengoptimuman akses ujian dengan gabungan BIST dan skim ujian luaran (CBET) dicadangkan untuk menghapuskan penggunaan bas ujian yang membazir. Kaedah ini boleh meminimumkan masa ujian dan menghapuskan penggunaan boros pin luaran dengan mempertimbangkan pertukaran antara masa ujian dan bilangan pin luaran. Idea kami terdiri daripada dua bahagian. Satu adalah untuk menentukan kumpulan optimum, setiap satunya terdiri daripada teras, untuk berkongsi mekanisme untuk ujian luaran secara serentak. Yang lain adalah untuk menentukan lebar jalur optimum input dan output luaran untuk ujian luaran. Idea kami pada asasnya dirumuskan untuk tujuan menghapuskan penggunaan pin luaran yang membazir. Kami menjadikan bahagian ujian luaran berada di bawah lebar jalur penuh pin luaran dengan mempertimbangkan pertukaran antara masa ujian dan bilangan pin luaran. Ini dicapai hanya dengan skim CBET kerana ia membenarkan set ujian untuk kedua-dua BIST dan ujian luaran menjadi anjal. Mengambil seni bina bas ujian sebagai contoh, rumusan untuk pengoptimuman akses ujian dan keputusan percubaan ditunjukkan. Keputusan eksperimen mendedahkan bahawa pengoptimuman kami boleh mencapai pengurangan 51.9% dalam masa ujian penjadualan ujian konvensional dan cadangan kami disahkan berkesan dalam mengurangkan masa ujian sistem-pada-cip.
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Salinan
Makoto SUGIHARA, Hiroto YASUURA, "Optimization of Test Accesses with a Combined BIST and External Test Scheme" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2731-2738, November 2001, doi: .
Abstract: External pins for tests are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architecture. When cores are tested via test buses which have constant bit widths, test stimuli and test responses for a particular core have to be transported over these test buses. The core might require more widths for input and output than test buses, and hence, for some part of the test, the TAMs are idle; this is a wasteful usage of the TAMs. In this paper, an optimization method of test accesses with a combined BIST and external test (CBET) scheme is proposed for eliminating the wasteful usage of test buses. This method can minimize the test time and eliminate the wasteful usage of external pins by considering the trade-off between test time and the number of external pins. Our idea consists of two parts. One is to determine the optimum groups, each of which consists of cores, to simultaneously share mechanisms for the external test. The other is to determine the optimum bandwidth of the external input and output for the external test. Our idea is basically formulated for the purpose of eliminating the wasteful external pin usage. We make the external test part to be under the full bandwidth of external pins by considering the trade-off between the test time and the number of external pins. This is achieved only with the CBET scheme because it permits test sets for both the BIST and the external test to be elastic. Taking test bus architecture as an example, a formulation for test access optimization and experimental results are shown. Experimental results reveal that our optimization can achieve a 51.9% reduction in the test time of conventional test scheduling and our proposals are confirmed to be effective in reducing the test time of system-on-a-chip.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2731/_p
Salinan
@ARTICLE{e84-a_11_2731,
author={Makoto SUGIHARA, Hiroto YASUURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Optimization of Test Accesses with a Combined BIST and External Test Scheme},
year={2001},
volume={E84-A},
number={11},
pages={2731-2738},
abstract={External pins for tests are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architecture. When cores are tested via test buses which have constant bit widths, test stimuli and test responses for a particular core have to be transported over these test buses. The core might require more widths for input and output than test buses, and hence, for some part of the test, the TAMs are idle; this is a wasteful usage of the TAMs. In this paper, an optimization method of test accesses with a combined BIST and external test (CBET) scheme is proposed for eliminating the wasteful usage of test buses. This method can minimize the test time and eliminate the wasteful usage of external pins by considering the trade-off between test time and the number of external pins. Our idea consists of two parts. One is to determine the optimum groups, each of which consists of cores, to simultaneously share mechanisms for the external test. The other is to determine the optimum bandwidth of the external input and output for the external test. Our idea is basically formulated for the purpose of eliminating the wasteful external pin usage. We make the external test part to be under the full bandwidth of external pins by considering the trade-off between the test time and the number of external pins. This is achieved only with the CBET scheme because it permits test sets for both the BIST and the external test to be elastic. Taking test bus architecture as an example, a formulation for test access optimization and experimental results are shown. Experimental results reveal that our optimization can achieve a 51.9% reduction in the test time of conventional test scheduling and our proposals are confirmed to be effective in reducing the test time of system-on-a-chip.},
keywords={},
doi={},
ISSN={},
month={November},}
Salinan
TY - JOUR
TI - Optimization of Test Accesses with a Combined BIST and External Test Scheme
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2731
EP - 2738
AU - Makoto SUGIHARA
AU - Hiroto YASUURA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - External pins for tests are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architecture. When cores are tested via test buses which have constant bit widths, test stimuli and test responses for a particular core have to be transported over these test buses. The core might require more widths for input and output than test buses, and hence, for some part of the test, the TAMs are idle; this is a wasteful usage of the TAMs. In this paper, an optimization method of test accesses with a combined BIST and external test (CBET) scheme is proposed for eliminating the wasteful usage of test buses. This method can minimize the test time and eliminate the wasteful usage of external pins by considering the trade-off between test time and the number of external pins. Our idea consists of two parts. One is to determine the optimum groups, each of which consists of cores, to simultaneously share mechanisms for the external test. The other is to determine the optimum bandwidth of the external input and output for the external test. Our idea is basically formulated for the purpose of eliminating the wasteful external pin usage. We make the external test part to be under the full bandwidth of external pins by considering the trade-off between the test time and the number of external pins. This is achieved only with the CBET scheme because it permits test sets for both the BIST and the external test to be elastic. Taking test bus architecture as an example, a formulation for test access optimization and experimental results are shown. Experimental results reveal that our optimization can achieve a 51.9% reduction in the test time of conventional test scheduling and our proposals are confirmed to be effective in reducing the test time of system-on-a-chip.
ER -