The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam kertas kerja ini kami membentangkan dua sumbangan untuk satu set transformasi tempatan (set pemilihan) untuk meningkatkan prestasi litar yang sangat besar. Sumbangan pertama ialah idea "nod padding" dan "set multi-separator. " Kami telah membuktikan bahawa gabungan nod padding dan set multi-separator menyediakan set pemilihan optimum. Sumbangan kedua ialah kaedah heuristik kami untuk mencari set berbilang pemisah separa optimum, yang menggunakan algoritma aliran rangkaian. Kaedah kami adalah teguh untuk litar yang sangat besar, kerana penggunaan memori dan masa pengiraannya adalah tertib linear dan polinomial dengan saiz litar. Kami telah membandingkan kaedah kami dengan kaedah fungsi pemilihan Singh, yang menyediakan set pemilihan optimum dan merupakan kaedah terbaik dalam literatur setakat ini. Kaedah kami telah berjaya mengoptimumkan kelewatan semua litar, manakala kaedah fungsi pemilihan Singh telah dibatalkan dengan tiga litar besar kerana limpahan memori. Keputusan juga telah menunjukkan kaedah kami mempunyai keupayaan yang setanding dalam pengoptimuman kelewatan dengan kaedah Singh, walaupun kaedah kami adalah heuristik.
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Salinan
Yutaka TAMIYA, "Robust Performance Optimization Using Padding Nodes and Separator Sets" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2739-2745, November 2001, doi: .
Abstract: In this paper we present two contributions for a set of local transformations (a selection set) to improve a performance of a very large circuit. The first contribution is an idea of "padding node" and "multi-separator-set. " We have proven that combination of padding node and multi-separator-set provides the optimum selection set. The second contribution is our heuristic method to find a semi-optimum multi-separator-set, which uses a network flow algorithm. Our method is robust for very large circuits, because its memory usage and calculation time are linear and polynomial order with the size of the circuit. We have compared our method with Singh's selection function method, which provides the optimum selection set and is the best method in literature to date. Our method has successfully optimized delays of all circuits, while Singh's selection function method has aborted with three large circuits because of memory overflow. The results also has shown our method has a comparable capability in delay optimization to Singh's method, although our method is heuristic.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2739/_p
Salinan
@ARTICLE{e84-a_11_2739,
author={Yutaka TAMIYA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Robust Performance Optimization Using Padding Nodes and Separator Sets},
year={2001},
volume={E84-A},
number={11},
pages={2739-2745},
abstract={In this paper we present two contributions for a set of local transformations (a selection set) to improve a performance of a very large circuit. The first contribution is an idea of "padding node" and "multi-separator-set. " We have proven that combination of padding node and multi-separator-set provides the optimum selection set. The second contribution is our heuristic method to find a semi-optimum multi-separator-set, which uses a network flow algorithm. Our method is robust for very large circuits, because its memory usage and calculation time are linear and polynomial order with the size of the circuit. We have compared our method with Singh's selection function method, which provides the optimum selection set and is the best method in literature to date. Our method has successfully optimized delays of all circuits, while Singh's selection function method has aborted with three large circuits because of memory overflow. The results also has shown our method has a comparable capability in delay optimization to Singh's method, although our method is heuristic.},
keywords={},
doi={},
ISSN={},
month={November},}
Salinan
TY - JOUR
TI - Robust Performance Optimization Using Padding Nodes and Separator Sets
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2739
EP - 2745
AU - Yutaka TAMIYA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - In this paper we present two contributions for a set of local transformations (a selection set) to improve a performance of a very large circuit. The first contribution is an idea of "padding node" and "multi-separator-set. " We have proven that combination of padding node and multi-separator-set provides the optimum selection set. The second contribution is our heuristic method to find a semi-optimum multi-separator-set, which uses a network flow algorithm. Our method is robust for very large circuits, because its memory usage and calculation time are linear and polynomial order with the size of the circuit. We have compared our method with Singh's selection function method, which provides the optimum selection set and is the best method in literature to date. Our method has successfully optimized delays of all circuits, while Singh's selection function method has aborted with three large circuits because of memory overflow. The results also has shown our method has a comparable capability in delay optimization to Singh's method, although our method is heuristic.
ER -