The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Abstrak-- Gelung berkunci fasa (PLL) digunakan secara meluas untuk pelbagai tujuan. Prestasi lokap adalah salah satu item sasaran terpenting dalam mereka bentuk PLL. Dalam PLL digital, sukar untuk mengawal kekerapan dan fasa secara bebas, yang menjadikannya sukar untuk meningkatkan prestasi penguncian. Litar kelewatan berubah-ubah yang melaraskan hanya fasa PLL diperkenalkan di sini. Simulasi model gelung penuh dengan kelewatan boleh dikawal terukur menunjukkan keberkesanan menggunakan kaedah pelarasan fasa dengan kelewatan berubah-ubah kepada PLL.
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Salinan
Takeo YASUDA, Hiroaki FUJITA, Hidetoshi ONODERA, "A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2793-2801, November 2001, doi: .
Abstract: Abstract-- Phase locked loop (PLL) is widely used for many purposes. The lock-up performance is one of the most important target items in designing PLLs. In a digital PLL, it is difficult to control the frequency and phase independently, which makes it difficult to improve lock-up performance. A variable delay circuit which adjusts only the phase of the PLL is introduced here. A full loop model simulation with measured controllable delay shows the effectiveness of applying the phase adjust method with the variable delay to the PLL.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2793/_p
Salinan
@ARTICLE{e84-a_11_2793,
author={Takeo YASUDA, Hiroaki FUJITA, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance},
year={2001},
volume={E84-A},
number={11},
pages={2793-2801},
abstract={Abstract-- Phase locked loop (PLL) is widely used for many purposes. The lock-up performance is one of the most important target items in designing PLLs. In a digital PLL, it is difficult to control the frequency and phase independently, which makes it difficult to improve lock-up performance. A variable delay circuit which adjusts only the phase of the PLL is introduced here. A full loop model simulation with measured controllable delay shows the effectiveness of applying the phase adjust method with the variable delay to the PLL.},
keywords={},
doi={},
ISSN={},
month={November},}
Salinan
TY - JOUR
TI - A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2793
EP - 2801
AU - Takeo YASUDA
AU - Hiroaki FUJITA
AU - Hidetoshi ONODERA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - Abstract-- Phase locked loop (PLL) is widely used for many purposes. The lock-up performance is one of the most important target items in designing PLLs. In a digital PLL, it is difficult to control the frequency and phase independently, which makes it difficult to improve lock-up performance. A variable delay circuit which adjusts only the phase of the PLL is introduced here. A full loop model simulation with measured controllable delay shows the effectiveness of applying the phase adjust method with the variable delay to the PLL.
ER -