The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Laporan ini menerangkan kaedah baharu untuk penempatan optimum kapasitor penyahgandingan pada papan litar bercetak (PCB). Kaedah ini mencari kedudukan optimum kapasitor penyahgandingan supaya ciri impedans pada bekalan kuasa diminimumkan dalam julat frekuensi yang ditentukan. Dalam kaedah ini, PCB dimodelkan oleh kaedah PEEC untuk mengendalikan struktur 3 dimensi dan teknik Krylov-subruang digunakan untuk mendapatkan ciri-ciri impedans dalam domain frekuensi dengan cekap.
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Salinan
Atsushi KAMO, Takayuki WATANABE, Hideki ASAI, "A New Methodology for Optimal Placement of Decoupling Capacitors on Printed Circuit Board" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 12, pp. 3177-3181, December 2001, doi: .
Abstract: This report describes a new methodology for the optimal placement of decoupling capacitors on the printed circuit board (PCB). This method searches the optimal position of decoupling capacitor so that the impedance characteristics at the power supply is minimized in the specified frequency range. In this method, the PCB is modeled by the PEEC method to handle the 3-dimensional structures and Krylov-subspace technique is applied to obtain efficiently the impedance characteristics in the frequency domain.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_12_3177/_p
Salinan
@ARTICLE{e84-a_12_3177,
author={Atsushi KAMO, Takayuki WATANABE, Hideki ASAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A New Methodology for Optimal Placement of Decoupling Capacitors on Printed Circuit Board},
year={2001},
volume={E84-A},
number={12},
pages={3177-3181},
abstract={This report describes a new methodology for the optimal placement of decoupling capacitors on the printed circuit board (PCB). This method searches the optimal position of decoupling capacitor so that the impedance characteristics at the power supply is minimized in the specified frequency range. In this method, the PCB is modeled by the PEEC method to handle the 3-dimensional structures and Krylov-subspace technique is applied to obtain efficiently the impedance characteristics in the frequency domain.},
keywords={},
doi={},
ISSN={},
month={December},}
Salinan
TY - JOUR
TI - A New Methodology for Optimal Placement of Decoupling Capacitors on Printed Circuit Board
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3177
EP - 3181
AU - Atsushi KAMO
AU - Takayuki WATANABE
AU - Hideki ASAI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2001
AB - This report describes a new methodology for the optimal placement of decoupling capacitors on the printed circuit board (PCB). This method searches the optimal position of decoupling capacitor so that the impedance characteristics at the power supply is minimized in the specified frequency range. In this method, the PCB is modeled by the PEEC method to handle the 3-dimensional structures and Krylov-subspace technique is applied to obtain efficiently the impedance characteristics in the frequency domain.
ER -