The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Seni bina lipat dan interpolasi analog kepada digital (ADC) mod semasa dengan penguat lipatan berganda dicadangkan dalam kertas ini. Penguat lipatan berganda mod semasa digunakan bukan sahaja untuk mengurangkan bilangan sumber arus rujukan, tetapi juga untuk mengurangkan pelesapan kuasa dalam ADC. ADC yang dicadangkan untuk 12 bit telah direka oleh proses poli/logam berganda CMOS 0.65 µm n-telaga. Hasil simulasi menunjukkan ketaklinear pembezaan (DNL) bagi
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Salinan
Hyung Hoon KIM, Kwang Sub YOON, "A Current-Mode Folding/Interpolating CMOS A/D Converter with Multiplied Folding Amplifiers" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 2, pp. 563-567, February 2001, doi: .
Abstract: A current-mode folding and interpolating analog to digital converter (ADC) architecture with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current source, but also to decrease a power dissipation within the ADC. The proposed ADC for 12 bit was designed by a 0.65 µm n-well CMOS single poly/double metal process. The simulated result shows a differential nonlinearity (DNL) of
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_2_563/_p
Salinan
@ARTICLE{e84-a_2_563,
author={Hyung Hoon KIM, Kwang Sub YOON, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Current-Mode Folding/Interpolating CMOS A/D Converter with Multiplied Folding Amplifiers},
year={2001},
volume={E84-A},
number={2},
pages={563-567},
abstract={A current-mode folding and interpolating analog to digital converter (ADC) architecture with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current source, but also to decrease a power dissipation within the ADC. The proposed ADC for 12 bit was designed by a 0.65 µm n-well CMOS single poly/double metal process. The simulated result shows a differential nonlinearity (DNL) of
keywords={},
doi={},
ISSN={},
month={February},}
Salinan
TY - JOUR
TI - A Current-Mode Folding/Interpolating CMOS A/D Converter with Multiplied Folding Amplifiers
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 563
EP - 567
AU - Hyung Hoon KIM
AU - Kwang Sub YOON
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2001
AB - A current-mode folding and interpolating analog to digital converter (ADC) architecture with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current source, but also to decrease a power dissipation within the ADC. The proposed ADC for 12 bit was designed by a 0.65 µm n-well CMOS single poly/double metal process. The simulated result shows a differential nonlinearity (DNL) of
ER -