The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini membentangkan pendekatan yang cekap untuk masalah pembahagian perkakasan/perisian: sintesis coprocessor khusus aplikasi yang mempercepatkan perisian terbenam berjalan pada pemproses utama. Memandangkan satu set graf aliran data (DFG), kebanyakan pendekatan pembahagian perkakasan/perisian sebelum ini telah memfokuskan pada pemetaan DFG kepada perkakasan atau perisian. Kelemahan biasa mereka ialah 1) mereka mengabaikan pelbagai alternatif pelaksanaan dalam merealisasikan DFG sebagai perkakasan berdasarkan andaian bahawa hanya satu pelaksanaan perkakasan wujud untuk DFG, dan bahawa 2) mereka tidak menganggap kesan penggabungan pada kawasan perkakasan semasa mensintesis. pemproses bersama dengan menggabungkan DFG. Untuk menangani isu pertama, kami merumuskan kedua-dua pemetaan DFG kepada perkakasan atau perisian dan pemilihan pelaksanaan perkakasan yang sesuai untuk setiap DFG sebagai masalah pengaturcaraan integer tunggal, dan kemudian menggunakan algoritma berulang berdasarkan heuristik Kernighan dan Lin untuk menyelesaikan masalah. Untuk mengurangkan masa CPU, kami telah merangka struktur data yang mengira kos pelaksanaan perkakasan dengan cepat. Untuk menangani isu kedua, kaedah kami memautkan DFG dengan nod tiruan untuk menghasilkan satu DFG besar, dan kemudian mensintesis pemproses bersama sasaran dengan menjadualkan DFG secara global dan memperuntukkan laluan datanya. Keputusan eksperimen menunjukkan bahawa pendekatan kami mengatasi pendekatan sebelumnya berdasarkan algoritma genetik (GA) dalam kedua-dua kawasan coprocessor dan masa CPU.
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Salinan
Dae-Hyun LEE, In-Cheol PARK, Chong-Min KYUNG, "Synthesis of Application-Specific Coprocessor for Core-Based ASIC Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 2, pp. 604-613, February 2001, doi: .
Abstract: This paper presents an efficient approach for a hardware/software partitioning problem: synthesis of an application-specific coprocessor which accelerates an embedded software running on a main processor. Given a set of data flow graphs (DFGs), most of previous hardware/software partitioning approaches have focused on mapping DFGs to hardware or software. Their common weaknesses are that 1) they ignore various implementation alternatives in realizing DFGs as hardware based on the assumption that only a single hardware implementation exists for a DFG, and that 2) they don't consider the effect of merging on hardware area when synthesizing a coprocessor by merging DFGs. To deal with the first issue, we formulate both the mapping of DFGs to hardware or software and the selection of the appropriate hardware implementation for each DFG as a single integer programming problem, and then apply an iterative algorithm based on the Kernighan and Lin's heuristic to solve the problem. To reduce the CPU time, we have devised data structures that quickly calculate costs of hardware implementations. To deal with the second issue, our method links DFGs with dummy nodes to produce a single large DFG, and then synthesizes a target coprocessor by globally scheduling the DFG and allocating its datapath. Experimental results demonstrate that our approach outperforms the previous approach based on genetic algorithm (GA) in both the coprocessor area and the CPU time.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_2_604/_p
Salinan
@ARTICLE{e84-a_2_604,
author={Dae-Hyun LEE, In-Cheol PARK, Chong-Min KYUNG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Synthesis of Application-Specific Coprocessor for Core-Based ASIC Design},
year={2001},
volume={E84-A},
number={2},
pages={604-613},
abstract={This paper presents an efficient approach for a hardware/software partitioning problem: synthesis of an application-specific coprocessor which accelerates an embedded software running on a main processor. Given a set of data flow graphs (DFGs), most of previous hardware/software partitioning approaches have focused on mapping DFGs to hardware or software. Their common weaknesses are that 1) they ignore various implementation alternatives in realizing DFGs as hardware based on the assumption that only a single hardware implementation exists for a DFG, and that 2) they don't consider the effect of merging on hardware area when synthesizing a coprocessor by merging DFGs. To deal with the first issue, we formulate both the mapping of DFGs to hardware or software and the selection of the appropriate hardware implementation for each DFG as a single integer programming problem, and then apply an iterative algorithm based on the Kernighan and Lin's heuristic to solve the problem. To reduce the CPU time, we have devised data structures that quickly calculate costs of hardware implementations. To deal with the second issue, our method links DFGs with dummy nodes to produce a single large DFG, and then synthesizes a target coprocessor by globally scheduling the DFG and allocating its datapath. Experimental results demonstrate that our approach outperforms the previous approach based on genetic algorithm (GA) in both the coprocessor area and the CPU time.},
keywords={},
doi={},
ISSN={},
month={February},}
Salinan
TY - JOUR
TI - Synthesis of Application-Specific Coprocessor for Core-Based ASIC Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 604
EP - 613
AU - Dae-Hyun LEE
AU - In-Cheol PARK
AU - Chong-Min KYUNG
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2001
AB - This paper presents an efficient approach for a hardware/software partitioning problem: synthesis of an application-specific coprocessor which accelerates an embedded software running on a main processor. Given a set of data flow graphs (DFGs), most of previous hardware/software partitioning approaches have focused on mapping DFGs to hardware or software. Their common weaknesses are that 1) they ignore various implementation alternatives in realizing DFGs as hardware based on the assumption that only a single hardware implementation exists for a DFG, and that 2) they don't consider the effect of merging on hardware area when synthesizing a coprocessor by merging DFGs. To deal with the first issue, we formulate both the mapping of DFGs to hardware or software and the selection of the appropriate hardware implementation for each DFG as a single integer programming problem, and then apply an iterative algorithm based on the Kernighan and Lin's heuristic to solve the problem. To reduce the CPU time, we have devised data structures that quickly calculate costs of hardware implementations. To deal with the second issue, our method links DFGs with dummy nodes to produce a single large DFG, and then synthesizes a target coprocessor by globally scheduling the DFG and allocating its datapath. Experimental results demonstrate that our approach outperforms the previous approach based on genetic algorithm (GA) in both the coprocessor area and the CPU time.
ER -