The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini membentangkan algoritma penghalaan prestasi dan kebolehhalauan baharu untuk tatasusunan gerbang boleh atur cara medan (FPGA) berasaskan tatasusunan simetri. Sumbangan kerja kami adalah untuk mengatasi salah satu batasan paling kritikal bagi algoritma penghalaan sebelumnya: anggaran ketumpatan penghalaan yang tidak tepat yang terlalu umum untuk FPGA simetri. Untuk tujuan ini, kami merancang langkah ketumpatan penghalaan baharu yang dikaitkan secara langsung dengan struktur (blok suis) FPGA simetri, dan menggunakannya secara konsisten dalam penghalaan global dan terperinci. Dengan penggunaan metrik penghalaan tepat yang dicadangkan, kami membangunkan algoritma penghalaan baharu yang dipanggil penghalaan berasaskan penguraian bersih yang boleh dipercayai yang sangat pantas, namun menghasilkan keputusan penghalaan yang sangat baik dari segi kelewatan bersih/laluan dan kebolehhalaan. Percubaan yang meluas telah dijalankan untuk menunjukkan keberkesanan algoritma kami berdasarkan metrik kos yang dicadangkan. Ringkasnya, jika dibandingkan dengan hasil yang paling terkenal dalam literatur (TRACER-fpga_PR dan SEGA), algoritma kami telah menunjukkan kelewatan laluan terpanjang 31.9% lebih pendek dan kelewatan bersih terpanjang 23.0% lebih pendek walaupun dengan masa pelaksanaan 9 kali lebih pantas.
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Salinan
Nak-Woong EUM, Inhag PARK, Chong-Min KYUNG, "An Efficient Routing Algorithm for Symmetrical FPGAs Using Reliable Cost Metrics" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 3, pp. 829-838, March 2001, doi: .
Abstract: This paper presents a new performance and routability-driven routing algorithm for symmetrical array-based field-programmable gate arrays (FPGAs). The contribution of our work is to overcome one of the most critical limitations of the previous routing algorithms: inaccurate estimations of routing density which were too general for symmetrical FPGA. To this end, we devised new routing density measures that are directly linked to the structure (switch block) of symmetrical FPGA, and utilize them consistently in global and detailed routings. With the use of the proposed accurate routing metrics, we developed a new routing algorithm called a reliable net decomposition-based routing which is very fast, and yet produces excellent routing results in terms of net/path delays and routability. An extensive experiment was carried out to show the effectiveness of our algorithm based on the proposed cost metrics. In summary, when compared to the best known results in the literature (TRACER-fpga_PR and SEGA), our algorithm has shown 31.9% shorter longest path delay and 23.0% shorter longest net delay even with about 9 times faster execution time.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_3_829/_p
Salinan
@ARTICLE{e84-a_3_829,
author={Nak-Woong EUM, Inhag PARK, Chong-Min KYUNG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Efficient Routing Algorithm for Symmetrical FPGAs Using Reliable Cost Metrics},
year={2001},
volume={E84-A},
number={3},
pages={829-838},
abstract={This paper presents a new performance and routability-driven routing algorithm for symmetrical array-based field-programmable gate arrays (FPGAs). The contribution of our work is to overcome one of the most critical limitations of the previous routing algorithms: inaccurate estimations of routing density which were too general for symmetrical FPGA. To this end, we devised new routing density measures that are directly linked to the structure (switch block) of symmetrical FPGA, and utilize them consistently in global and detailed routings. With the use of the proposed accurate routing metrics, we developed a new routing algorithm called a reliable net decomposition-based routing which is very fast, and yet produces excellent routing results in terms of net/path delays and routability. An extensive experiment was carried out to show the effectiveness of our algorithm based on the proposed cost metrics. In summary, when compared to the best known results in the literature (TRACER-fpga_PR and SEGA), our algorithm has shown 31.9% shorter longest path delay and 23.0% shorter longest net delay even with about 9 times faster execution time.},
keywords={},
doi={},
ISSN={},
month={March},}
Salinan
TY - JOUR
TI - An Efficient Routing Algorithm for Symmetrical FPGAs Using Reliable Cost Metrics
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 829
EP - 838
AU - Nak-Woong EUM
AU - Inhag PARK
AU - Chong-Min KYUNG
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2001
AB - This paper presents a new performance and routability-driven routing algorithm for symmetrical array-based field-programmable gate arrays (FPGAs). The contribution of our work is to overcome one of the most critical limitations of the previous routing algorithms: inaccurate estimations of routing density which were too general for symmetrical FPGA. To this end, we devised new routing density measures that are directly linked to the structure (switch block) of symmetrical FPGA, and utilize them consistently in global and detailed routings. With the use of the proposed accurate routing metrics, we developed a new routing algorithm called a reliable net decomposition-based routing which is very fast, and yet produces excellent routing results in terms of net/path delays and routability. An extensive experiment was carried out to show the effectiveness of our algorithm based on the proposed cost metrics. In summary, when compared to the best known results in the literature (TRACER-fpga_PR and SEGA), our algorithm has shown 31.9% shorter longest path delay and 23.0% shorter longest net delay even with about 9 times faster execution time.
ER -