The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Gabungan perisian dan pelaksanaan perkakasan sistolik untuk algoritma pemampatan Aritmetik Kuasi dibentangkan. Perkakasan dilaksanakan sebagai pelaksanaan perkakasan saluran paip. Pelaksanaan tidak mengubah algoritma. Ia hanya membahagikannya kepada dua bahagian. Gabungan perisian selari dan perkakasan saluran paip boleh memberikan pemampatan yang sangat pantas tanpa penurunan kecekapan pemampatan.
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Salinan
Yair WISEMAN, "A Pipeline Chip for Quasi Arithmetic Coding" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 4, pp. 1034-1041, April 2001, doi: .
Abstract: A combination of a software and a systolic hardware implementation for the Quasi Arithmetic compression algorithm is presented. The hardware is implemented as a pipeline hardware implementation. The implementation doesn't change the the algorithm. It just split it into two parts. The combination of parallel software and pipeline hardware can give very fast compression without decline of the compression efficiency.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_4_1034/_p
Salinan
@ARTICLE{e84-a_4_1034,
author={Yair WISEMAN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Pipeline Chip for Quasi Arithmetic Coding},
year={2001},
volume={E84-A},
number={4},
pages={1034-1041},
abstract={A combination of a software and a systolic hardware implementation for the Quasi Arithmetic compression algorithm is presented. The hardware is implemented as a pipeline hardware implementation. The implementation doesn't change the the algorithm. It just split it into two parts. The combination of parallel software and pipeline hardware can give very fast compression without decline of the compression efficiency.},
keywords={},
doi={},
ISSN={},
month={April},}
Salinan
TY - JOUR
TI - A Pipeline Chip for Quasi Arithmetic Coding
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1034
EP - 1041
AU - Yair WISEMAN
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2001
AB - A combination of a software and a systolic hardware implementation for the Quasi Arithmetic compression algorithm is presented. The hardware is implemented as a pipeline hardware implementation. The implementation doesn't change the the algorithm. It just split it into two parts. The combination of parallel software and pipeline hardware can give very fast compression without decline of the compression efficiency.
ER -