The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kenangan cache ialah ingatan cepat kecil yang digunakan untuk menyimpan sementara kandungan memori utama yang mungkin dirujuk oleh pemproses supaya mengurangkan masa arahan dan akses data. Dalam kajian prestasi cache, kebanyakan kerja terdahulu telah menggunakan kaedah berasaskan simulasi. Walau bagaimanapun, penyelidikan seperti itu tidak dapat menjelaskan keputusan yang diperolehi dengan tepat. Selain itu, apabila pemproses baharu direka bentuk, simulasi besar mesti dilakukan semula dengan beberapa parameter berbeza. Penyelidikan ini mengklasifikasikan struktur cache untuk pemproses superscalar kepada empat jenis, dan kemudian mewakili model analisis proses pengambilan arahan untuk setiap jenis cache dengan mengambil kira pelbagai jenis parameter seni bina seperti kekerapan arahan cawangan dalam program, kadar kehilangan cache, penalti kehilangan cache, cawangan. kekerapan salah ramal, dan penalti salah ramal cawangan, dan lain-lain. Untuk membuktikan ketepatan model yang dicadangkan, kami melakukan simulasi yang meluas dan membandingkan keputusan dengan model analisis. Keputusan simulasi menunjukkan bahawa model yang dicadangkan boleh menganggarkan kadar pengambilan arahan yang dijangkakan dengan tepat dalam ralat 10% dalam kebanyakan kes. Makalah ini menunjukkan bahawa peningkatan kesilapan cache mengurangkan kadar pengambilan arahan dengan lebih teruk daripada kesilapan ramalan cawangan. Model ini juga dapat memberikan hubungan yang tepat antara cache miss dan salah ramal cawangan untuk analisis pengambilan arahan. Model yang dicadangkan boleh menjelaskan punca kemerosotan prestasi yang tidak dapat didedahkan dengan kaedah simulasi sahaja.
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Salinan
Sun-Mo KIM, Jung-Woo LEE, Soo-Haeng LEE, Sang-Bang CHOI, "Analytical Models and Performance Analyses of Instruction Fetch on Superscalar Processors" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 6, pp. 1442-1453, June 2001, doi: .
Abstract: Cache memories are small fast memories used to temporarily hold the contents of main memory that are likely to be referenced by processors so as to reduce instruction and data access time. In study of cache performance, most of previous works have employed simulation-based methods. However, that kind of researches cannot precisely explain the obtained results. Moreover, when a new processor is designed, huge simulations must be performed again with several different parameters. This research classifies cache structures for superscalar processors into four types, and then represents analytical model of instruction fetch process for each cache type considering various kinds of architectural parameters such as the frequency of branch instructions in program, cache miss rate, cache miss penalty, branch misprediction frequency, and branch misprediction penalty, and etc. To prove the correctness of the proposed models, we performed extensive simulations and compared the results with the analytical models. Simulation results showed that the proposed model can estimate the expected instruction fetch rate accurately within 10% error in most cases. This paper shows that the increase of cache misses reduces the instruction fetch rate more severely than that of branch misprediction does. The model is also able to provide exact relationship between cache miss and branch misprediction for the instruction fetch analysis. The proposed model can explain the causes of performance degradation that cannot be uncovered by the simulation method only.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_6_1442/_p
Salinan
@ARTICLE{e84-a_6_1442,
author={Sun-Mo KIM, Jung-Woo LEE, Soo-Haeng LEE, Sang-Bang CHOI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Analytical Models and Performance Analyses of Instruction Fetch on Superscalar Processors},
year={2001},
volume={E84-A},
number={6},
pages={1442-1453},
abstract={Cache memories are small fast memories used to temporarily hold the contents of main memory that are likely to be referenced by processors so as to reduce instruction and data access time. In study of cache performance, most of previous works have employed simulation-based methods. However, that kind of researches cannot precisely explain the obtained results. Moreover, when a new processor is designed, huge simulations must be performed again with several different parameters. This research classifies cache structures for superscalar processors into four types, and then represents analytical model of instruction fetch process for each cache type considering various kinds of architectural parameters such as the frequency of branch instructions in program, cache miss rate, cache miss penalty, branch misprediction frequency, and branch misprediction penalty, and etc. To prove the correctness of the proposed models, we performed extensive simulations and compared the results with the analytical models. Simulation results showed that the proposed model can estimate the expected instruction fetch rate accurately within 10% error in most cases. This paper shows that the increase of cache misses reduces the instruction fetch rate more severely than that of branch misprediction does. The model is also able to provide exact relationship between cache miss and branch misprediction for the instruction fetch analysis. The proposed model can explain the causes of performance degradation that cannot be uncovered by the simulation method only.},
keywords={},
doi={},
ISSN={},
month={June},}
Salinan
TY - JOUR
TI - Analytical Models and Performance Analyses of Instruction Fetch on Superscalar Processors
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1442
EP - 1453
AU - Sun-Mo KIM
AU - Jung-Woo LEE
AU - Soo-Haeng LEE
AU - Sang-Bang CHOI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2001
AB - Cache memories are small fast memories used to temporarily hold the contents of main memory that are likely to be referenced by processors so as to reduce instruction and data access time. In study of cache performance, most of previous works have employed simulation-based methods. However, that kind of researches cannot precisely explain the obtained results. Moreover, when a new processor is designed, huge simulations must be performed again with several different parameters. This research classifies cache structures for superscalar processors into four types, and then represents analytical model of instruction fetch process for each cache type considering various kinds of architectural parameters such as the frequency of branch instructions in program, cache miss rate, cache miss penalty, branch misprediction frequency, and branch misprediction penalty, and etc. To prove the correctness of the proposed models, we performed extensive simulations and compared the results with the analytical models. Simulation results showed that the proposed model can estimate the expected instruction fetch rate accurately within 10% error in most cases. This paper shows that the increase of cache misses reduces the instruction fetch rate more severely than that of branch misprediction does. The model is also able to provide exact relationship between cache miss and branch misprediction for the instruction fetch analysis. The proposed model can explain the causes of performance degradation that cannot be uncovered by the simulation method only.
ER -