The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kaedah reka bentuk boleh diuji IDDQ baharu dicadangkan untuk litar PLA CMOS statik. Litar PLA jenis NOR-NOR yang boleh diuji direka bentuk menggunakan kaedah ini. Ditunjukkan bahawa semua ralat penyambung dalam satah NOR bagi litar PLA reka bentuk yang boleh diuji boleh dikesan melalui ujian IDDQ dengan 4 set vektor input ujian. Vektor input ujian adalah bebas daripada fungsi logik yang akan direalisasikan dalam litar PLA. Litar PLA direka bentuk menggunakan kaedah ini supaya arus bekalan senyap yang dijana apabila ia diuji akan menjadi sifar. Oleh itu, resolusi tinggi ujian IDDQ untuk litar PLA boleh diperoleh dengan menggunakan kaedah reka bentuk yang boleh diuji. Keputusan ujian IDDQ bagi litar PLA yang direka menggunakan kaedah reka bentuk yang boleh diuji ini tidak mengesahkan bahawa output yang dijangkakan boleh dijana daripada litar tetapi bahawa litar dibuat tanpa kesalahan merapatkan dalam satah NOR. Memandangkan ralat penyambung sering berlaku dalam fabrikasi IC yang canggih, reka bentuk yang boleh diuji adalah amat diperlukan untuk merealisasikan sistem logik yang sangat boleh dipercayai.
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Salinan
Masaki HASHIZUME, Hiroshi HOSHIKA, Hiroyuki YOTSUYANAGI, Takeomi TAMESADA, "Testable Static CMOS PLA for IDDQ Testing" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 6, pp. 1488-1495, June 2001, doi: .
Abstract: A new IDDQ testable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of NOR-NOR type is designed using this method. It is shown that all bridging faults in NOR planes of the testable designed PLA circuit can be detected by IDDQ testing with 4 sets of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed using this method so that the quiescent supply current generated when they are tested will be zero. Thus, high resolution of IDDQ tests for the PLA circuits can be obtained by using the testable design method. Results of IDDQ tests of PLA circuits designed using this testable design method confirm not that the expected output can be generated from the circuits but that the circuits are fabricated without bridging faults in NOR planes. Since bridging faults often occur in state-of-the-art IC fabrication, the testable design is indispensable for realizing highly reliable logic systems.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_6_1488/_p
Salinan
@ARTICLE{e84-a_6_1488,
author={Masaki HASHIZUME, Hiroshi HOSHIKA, Hiroyuki YOTSUYANAGI, Takeomi TAMESADA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Testable Static CMOS PLA for IDDQ Testing},
year={2001},
volume={E84-A},
number={6},
pages={1488-1495},
abstract={A new IDDQ testable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of NOR-NOR type is designed using this method. It is shown that all bridging faults in NOR planes of the testable designed PLA circuit can be detected by IDDQ testing with 4 sets of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed using this method so that the quiescent supply current generated when they are tested will be zero. Thus, high resolution of IDDQ tests for the PLA circuits can be obtained by using the testable design method. Results of IDDQ tests of PLA circuits designed using this testable design method confirm not that the expected output can be generated from the circuits but that the circuits are fabricated without bridging faults in NOR planes. Since bridging faults often occur in state-of-the-art IC fabrication, the testable design is indispensable for realizing highly reliable logic systems.},
keywords={},
doi={},
ISSN={},
month={June},}
Salinan
TY - JOUR
TI - Testable Static CMOS PLA for IDDQ Testing
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1488
EP - 1495
AU - Masaki HASHIZUME
AU - Hiroshi HOSHIKA
AU - Hiroyuki YOTSUYANAGI
AU - Takeomi TAMESADA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2001
AB - A new IDDQ testable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of NOR-NOR type is designed using this method. It is shown that all bridging faults in NOR planes of the testable designed PLA circuit can be detected by IDDQ testing with 4 sets of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed using this method so that the quiescent supply current generated when they are tested will be zero. Thus, high resolution of IDDQ tests for the PLA circuits can be obtained by using the testable design method. Results of IDDQ tests of PLA circuits designed using this testable design method confirm not that the expected output can be generated from the circuits but that the circuits are fabricated without bridging faults in NOR planes. Since bridging faults often occur in state-of-the-art IC fabrication, the testable design is indispensable for realizing highly reliable logic systems.
ER -