The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Untuk mereka bentuk kelajuan tinggi m-bit litar penyongsangan selari ke atas GF(2m), kami mengkaji dua variasi untuk operasi pengulangan formula berangka, AB2, dalam menggaji segi empat sama dahulu and darab-dahulu operasi jenis. Daripada dua variasi yang dicadangkan, kami mencadangkan empat seni bina penyongsangan, menggunakan pengganda dan kuasa dua dalam [10], seperti berikut: seni bina separa sistolik duplikasi mudah untuk litar penyongsangan darab pertama (MFIC), seni bina separa sistolik selari m-bit untuk MFIC, seni bina separa sistolik duplikasi mudah untuk litar penyongsangan kuasa dua pertama (SFIC), dan seni bina separa sistolik selari m-bit dipermudahkan untuk SFIC. Antaranya, prestasi yang dipermudahkan mSeni bina separa sistolik -bit selari untuk SFIC disyorkan untuk aplikasi berkelajuan tinggi untuk mendapatkan daya pemprosesan maksimum dalam erti kata kerumitan perkakasan kecil dan kependaman rendah. Apabila kita melaksanakan dipermudahkan seni bina separa sistolik selari 8-bit untuk SFIC atas GF(28) dengan menggunakan perpustakaan CMOS 0.25 µm, diperlukan 2495 get logik dan 1848 selak, dan kependaman ialah 56 dan anggaran kadar jam ialah 580 MHz pada 100% daya pemprosesan.
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Salinan
Sungsoo CHOI, Kiseon KIM, "VLSI Architectures for High-Speed m-Bit Parallel Inversion in GF(2m) over Standard Basis" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 11, pp. 2468-2478, November 2002, doi: .
Abstract: To design a high-speed m-bit parallel inversion circuit over GF(2m), we study two variations for the repetition-operation of the numerical formula, AB2, in employing square-first and multiply-first type operations. From the proposed two variations, we propose four inversion architectures, adopting the multiplier and square in [10], as follows: simple duplication semi-systolic architecture for multiply-first inversion circuit (MFIC), m-bit parallel semi-systolic architecture for MFIC, simple duplication semi-systolic architecture for square-first inversion circuit (SFIC), and simplified m-bit parallel semi-systolic architecture for SFIC. Among them, performance of the simplified m-bit parallel semi-systolic architecture for SFIC is recommended for a high-speed applications to get a maximum throughput in the sense of small hardware-complexity, and low latency. When we implement the simplified 8-bit parallel semi-systolic architecture for SFIC over GF(28) by using 0.25 µm CMOS library, necessary are 2495 logic-gates and 1848 latches, and the latency is 56 and the estimated clock-rate is 580 MHz at 100% throughput.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_11_2468/_p
Salinan
@ARTICLE{e85-a_11_2468,
author={Sungsoo CHOI, Kiseon KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VLSI Architectures for High-Speed m-Bit Parallel Inversion in GF(2m) over Standard Basis},
year={2002},
volume={E85-A},
number={11},
pages={2468-2478},
abstract={To design a high-speed m-bit parallel inversion circuit over GF(2m), we study two variations for the repetition-operation of the numerical formula, AB2, in employing square-first and multiply-first type operations. From the proposed two variations, we propose four inversion architectures, adopting the multiplier and square in [10], as follows: simple duplication semi-systolic architecture for multiply-first inversion circuit (MFIC), m-bit parallel semi-systolic architecture for MFIC, simple duplication semi-systolic architecture for square-first inversion circuit (SFIC), and simplified m-bit parallel semi-systolic architecture for SFIC. Among them, performance of the simplified m-bit parallel semi-systolic architecture for SFIC is recommended for a high-speed applications to get a maximum throughput in the sense of small hardware-complexity, and low latency. When we implement the simplified 8-bit parallel semi-systolic architecture for SFIC over GF(28) by using 0.25 µm CMOS library, necessary are 2495 logic-gates and 1848 latches, and the latency is 56 and the estimated clock-rate is 580 MHz at 100% throughput.},
keywords={},
doi={},
ISSN={},
month={November},}
Salinan
TY - JOUR
TI - VLSI Architectures for High-Speed m-Bit Parallel Inversion in GF(2m) over Standard Basis
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2468
EP - 2478
AU - Sungsoo CHOI
AU - Kiseon KIM
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2002
AB - To design a high-speed m-bit parallel inversion circuit over GF(2m), we study two variations for the repetition-operation of the numerical formula, AB2, in employing square-first and multiply-first type operations. From the proposed two variations, we propose four inversion architectures, adopting the multiplier and square in [10], as follows: simple duplication semi-systolic architecture for multiply-first inversion circuit (MFIC), m-bit parallel semi-systolic architecture for MFIC, simple duplication semi-systolic architecture for square-first inversion circuit (SFIC), and simplified m-bit parallel semi-systolic architecture for SFIC. Among them, performance of the simplified m-bit parallel semi-systolic architecture for SFIC is recommended for a high-speed applications to get a maximum throughput in the sense of small hardware-complexity, and low latency. When we implement the simplified 8-bit parallel semi-systolic architecture for SFIC over GF(28) by using 0.25 µm CMOS library, necessary are 2495 logic-gates and 1848 latches, and the latency is 56 and the estimated clock-rate is 580 MHz at 100% throughput.
ER -