The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam kertas ini, kami telah mencadangkan kaedah penjanaan ujian peringkat tinggi yang cekap untuk litar tak segerak. Penjanaan ujian adalah berdasarkan tahap spesifikasi, terutamanya pada Graf Peralihan Isyarat (STG), yang merupakan sejenis kaedah spesifikasi untuk litar tak segerak. Kami mentakrifkan model kerosakan peringkat tinggi, yang dipanggil model Kesalahan Peralihan Negeri (STF) tunggal pada STG. Corak ujian untuk STF dijana berdasarkan Graf Keadaan Stabil (SSG), yang boleh diperoleh daripada STG secara langsung. Ruang keadaan yang diterokai dalam penjanaan ujian sangat berkurangan dan oleh itu kos penjanaan ujian adalah kecil dari segi masa pelaksanaan. Untuk meningkatkan liputan kerosakan pada peringkat pintu, kami juga telah mencadangkan model STF (ESTF) lanjutan dengan maklumat peringkat pintu tambahan. Keputusan eksperimen menunjukkan bahawa ujian yang dijana untuk STF mencapai liputan kerosakan yang tinggi dengan kos yang rendah untuk kerosakan terperangkap tunggal bagi litar aras get tersintesis yang sepadan. Ujian yang dijana untuk ESTF mencapai liputan kerosakan yang lebih tinggi dengan penanda aras yang sama dalam kos masa pelaksanaan yang lebih lama. Selanjutnya, kami juga telah mencadangkan penjanaan ujian 3 fasa berdasarkan kaedah yang dicadangkan di atas. Penjanaan ujian yang berkesan dilaksanakan oleh 3 fasa: 1) penjanaan ujian untuk STF, 2) penjanaan ujian untuk ESTF, dan 3) penjanaan ujian menggunakan kaedah lintasan mesin produk tak segerak. Keputusan eksperimen juga menunjukkan bahawa penjanaan ujian 3 fasa yang dicadangkan mencapai liputan kerosakan yang lebih tinggi dalam kos masa pelaksanaan yang lebih lama.
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Salinan
Eunjung OH, Soo-Hyun KIM, Dong-Ik LEE, Ho-Yong CHOI, "High-Level Test Generation for Asynchronous Circuits from Signal Transition Graph" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2674-2683, December 2002, doi: .
Abstract: In this paper, we have proposed an efficient high-level test generation method for asynchronous circuits. The test generation is based on specification level, especially on Signal Transition Graph (STG), which is a kind of specification method for asynchronous circuits. We define a high-level fault model, called a single State Transition Fault (STF) model on STG. Test patterns for STFs are generated based on Stable State Graph (SSG), which can be derived from STG directly. The state space explored in test generation is greatly reduced and hence the test generation cost is small in terms of execution time. To enhance the fault coverage at gate-level, we have also proposed an extended STF (ESTF) model with additional gate-level information. Experimental results show that the generated test for STFs achieves high fault coverage with low cost for single stuck-at faults of its corresponding synthesized gate-level circuit. The generated test for ESTFs attains higher fault coverage with same benchmark in cost of longer execution time. Further, we have also proposed a 3-phase test generation based on the above proposed methods. An effective test generation is implemented by 3-phase: 1) test generation for STFs, 2) test generation for ESTFs, and 3) test generation using an asynchronous product machine traversal method. Experimental results also show that the proposed 3-phase test generation achieves higher fault coverage in cost of longer execution time.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2674/_p
Salinan
@ARTICLE{e85-a_12_2674,
author={Eunjung OH, Soo-Hyun KIM, Dong-Ik LEE, Ho-Yong CHOI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Level Test Generation for Asynchronous Circuits from Signal Transition Graph},
year={2002},
volume={E85-A},
number={12},
pages={2674-2683},
abstract={In this paper, we have proposed an efficient high-level test generation method for asynchronous circuits. The test generation is based on specification level, especially on Signal Transition Graph (STG), which is a kind of specification method for asynchronous circuits. We define a high-level fault model, called a single State Transition Fault (STF) model on STG. Test patterns for STFs are generated based on Stable State Graph (SSG), which can be derived from STG directly. The state space explored in test generation is greatly reduced and hence the test generation cost is small in terms of execution time. To enhance the fault coverage at gate-level, we have also proposed an extended STF (ESTF) model with additional gate-level information. Experimental results show that the generated test for STFs achieves high fault coverage with low cost for single stuck-at faults of its corresponding synthesized gate-level circuit. The generated test for ESTFs attains higher fault coverage with same benchmark in cost of longer execution time. Further, we have also proposed a 3-phase test generation based on the above proposed methods. An effective test generation is implemented by 3-phase: 1) test generation for STFs, 2) test generation for ESTFs, and 3) test generation using an asynchronous product machine traversal method. Experimental results also show that the proposed 3-phase test generation achieves higher fault coverage in cost of longer execution time.},
keywords={},
doi={},
ISSN={},
month={December},}
Salinan
TY - JOUR
TI - High-Level Test Generation for Asynchronous Circuits from Signal Transition Graph
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2674
EP - 2683
AU - Eunjung OH
AU - Soo-Hyun KIM
AU - Dong-Ik LEE
AU - Ho-Yong CHOI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - In this paper, we have proposed an efficient high-level test generation method for asynchronous circuits. The test generation is based on specification level, especially on Signal Transition Graph (STG), which is a kind of specification method for asynchronous circuits. We define a high-level fault model, called a single State Transition Fault (STF) model on STG. Test patterns for STFs are generated based on Stable State Graph (SSG), which can be derived from STG directly. The state space explored in test generation is greatly reduced and hence the test generation cost is small in terms of execution time. To enhance the fault coverage at gate-level, we have also proposed an extended STF (ESTF) model with additional gate-level information. Experimental results show that the generated test for STFs achieves high fault coverage with low cost for single stuck-at faults of its corresponding synthesized gate-level circuit. The generated test for ESTFs attains higher fault coverage with same benchmark in cost of longer execution time. Further, we have also proposed a 3-phase test generation based on the above proposed methods. An effective test generation is implemented by 3-phase: 1) test generation for STFs, 2) test generation for ESTFs, and 3) test generation using an asynchronous product machine traversal method. Experimental results also show that the proposed 3-phase test generation achieves higher fault coverage in cost of longer execution time.
ER -