The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam beberapa penyelidikan dalam beberapa tahun kebelakangan ini, ia menunjukkan bahawa litar frekuensi jam yang lebih tinggi boleh diperolehi dengan mengawal pemasaan input jam setiap daftar. Walau bagaimanapun, penggunaan kuasa pokok jam yang diperolehi oleh mereka cenderung lebih besar kerana lokasi daftar tidak diambil kira dengan baik dalam penjadualan jam. Dalam makalah ini, kami mencadangkan sintesis pokok jam baru yang mencapai kedua-dua kekerapan jam yang lebih tinggi dan penggunaan kuasa yang lebih rendah. Algoritma yang dicadangkan kami menentukan pemasaan input jam daftar langkah demi langkah dalam membina struktur pokok jam. Pertama, tempoh jam litar diperbaiki dengan mengawal pemasaan input jam setiap daftar, dan kedua, pemasaan input jam diubah suai untuk membina pokok jam kuasa rendah tanpa merosot tempoh jam yang diperolehi. Menurut eksperimen kami menggunakan beberapa litar penanda aras, penggunaan kuasa pokok jam kami mencapai kira-kira 9.5% lebih kecil daripada kaedah sebelumnya.
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Salinan
Keiichi KUROKAWA, Takuya YASUI, Yoichi MATSUMURA, Masahiko TOYONAGA, Atsushi TAKAHASHI, "A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2746-2755, December 2002, doi: .
Abstract: In several researches in recent years, it is shown that the circuit of a higher clock frequency can be obtained by controlling the clock-input timing of each register. However, the power consumption of the clock-tree obtained by them tends to be larger since the locations of registers are not well taken into account in clock scheduling. In this paper, we propose a novel clock tree synthesis that attains both the higher clock frequency and the lower power consumption. Our proposed algorithm determines the clock-input timings of registers step by step in constructing a clock tree structure. First, the clock period of a circuit is improved by controlling the clock-input timing of each register, and second, the clock-input timings are modified to construct a low power clock tree without deteriorating the obtained clock period. According to our experiments using several benchmark circuits, the power consumption of our clock trees attain about 9.5% smaller than previous methods.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2746/_p
Salinan
@ARTICLE{e85-a_12_2746,
author={Keiichi KUROKAWA, Takuya YASUI, Yoichi MATSUMURA, Masahiko TOYONAGA, Atsushi TAKAHASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling},
year={2002},
volume={E85-A},
number={12},
pages={2746-2755},
abstract={In several researches in recent years, it is shown that the circuit of a higher clock frequency can be obtained by controlling the clock-input timing of each register. However, the power consumption of the clock-tree obtained by them tends to be larger since the locations of registers are not well taken into account in clock scheduling. In this paper, we propose a novel clock tree synthesis that attains both the higher clock frequency and the lower power consumption. Our proposed algorithm determines the clock-input timings of registers step by step in constructing a clock tree structure. First, the clock period of a circuit is improved by controlling the clock-input timing of each register, and second, the clock-input timings are modified to construct a low power clock tree without deteriorating the obtained clock period. According to our experiments using several benchmark circuits, the power consumption of our clock trees attain about 9.5% smaller than previous methods.},
keywords={},
doi={},
ISSN={},
month={December},}
Salinan
TY - JOUR
TI - A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2746
EP - 2755
AU - Keiichi KUROKAWA
AU - Takuya YASUI
AU - Yoichi MATSUMURA
AU - Masahiko TOYONAGA
AU - Atsushi TAKAHASHI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - In several researches in recent years, it is shown that the circuit of a higher clock frequency can be obtained by controlling the clock-input timing of each register. However, the power consumption of the clock-tree obtained by them tends to be larger since the locations of registers are not well taken into account in clock scheduling. In this paper, we propose a novel clock tree synthesis that attains both the higher clock frequency and the lower power consumption. Our proposed algorithm determines the clock-input timings of registers step by step in constructing a clock tree structure. First, the clock period of a circuit is improved by controlling the clock-input timing of each register, and second, the clock-input timings are modified to construct a low power clock tree without deteriorating the obtained clock period. According to our experiments using several benchmark circuits, the power consumption of our clock trees attain about 9.5% smaller than previous methods.
ER -