The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Selain ralat bait tunggal yang disebabkan oleh kegagalan cip tunggal, memori semikonduktor yang digunakan dalam sesetengah aplikasi, seperti sistem memori satelit, sangat terdedah kepada ralat bit berganda rawak. Oleh itu, adalah perlu untuk mereka bentuk Pembetulan Ralat Bit Ganda--Tunggal b-sedikit bait Pembetulan Ralat (DEC-SbEC) yang membetulkan kedua-dua ralat bit berganda rawak dan tunggal b-sedikit ralat bait. Surat-menyurat ini mencadangkan kelas DEC-S generikbKod EC yang boleh digunakan pada sistem memori komputer menggunakan cip DRAM berketumpatan tinggi terkini dengan data I/O lebar, seperti, 8, 16 atau 32 bit setiap cip. DEC-S yang dicadangkan8Kod EC sesuai untuk sistem memori menggunakan cip DRAM dengan data I/O 8-bit, dan memerlukan 24 bit semak untuk panjang maklumat praktikal seperti 64 dan 128 bit.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Salinan
Ganesan UMANESAN, Eiji FUJIWARA, "Random Double Bit Error Correcting--Single b-bit Byte Error Correcting (DEC-SbEC) Codes for Memory Systems" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 1, pp. 273-276, January 2002, doi: .
Abstract: Besides single byte errors which are caused by single chip failures, semiconductor memories used in some applications, such as satellite memory systems, are highly vulnerable to random double bit errors. It is therefore necessary to design Double bit Error Correcting--Single b-bit byte Error Correcting (DEC-SbEC) codes which correct both random double bit errors and single b-bit byte errors. This correspondence proposes a class of generic DEC-SbEC codes that are applicable to computer memory systems using recent high density DRAM chips with wide I/O data, such as, 8, 16 or 32 bits per chip. The proposed DEC-S8EC codes are suitable for memory systems using DRAM chips with 8-bit I/O data, and require 24 check bits for practical information lengths such as 64 and 128 bits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_1_273/_p
Salinan
@ARTICLE{e85-a_1_273,
author={Ganesan UMANESAN, Eiji FUJIWARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Random Double Bit Error Correcting--Single b-bit Byte Error Correcting (DEC-SbEC) Codes for Memory Systems},
year={2002},
volume={E85-A},
number={1},
pages={273-276},
abstract={Besides single byte errors which are caused by single chip failures, semiconductor memories used in some applications, such as satellite memory systems, are highly vulnerable to random double bit errors. It is therefore necessary to design Double bit Error Correcting--Single b-bit byte Error Correcting (DEC-SbEC) codes which correct both random double bit errors and single b-bit byte errors. This correspondence proposes a class of generic DEC-SbEC codes that are applicable to computer memory systems using recent high density DRAM chips with wide I/O data, such as, 8, 16 or 32 bits per chip. The proposed DEC-S8EC codes are suitable for memory systems using DRAM chips with 8-bit I/O data, and require 24 check bits for practical information lengths such as 64 and 128 bits.},
keywords={},
doi={},
ISSN={},
month={January},}
Salinan
TY - JOUR
TI - Random Double Bit Error Correcting--Single b-bit Byte Error Correcting (DEC-SbEC) Codes for Memory Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 273
EP - 276
AU - Ganesan UMANESAN
AU - Eiji FUJIWARA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2002
AB - Besides single byte errors which are caused by single chip failures, semiconductor memories used in some applications, such as satellite memory systems, are highly vulnerable to random double bit errors. It is therefore necessary to design Double bit Error Correcting--Single b-bit byte Error Correcting (DEC-SbEC) codes which correct both random double bit errors and single b-bit byte errors. This correspondence proposes a class of generic DEC-SbEC codes that are applicable to computer memory systems using recent high density DRAM chips with wide I/O data, such as, 8, 16 or 32 bits per chip. The proposed DEC-S8EC codes are suitable for memory systems using DRAM chips with 8-bit I/O data, and require 24 check bits for practical information lengths such as 64 and 128 bits.
ER -