The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Pengganda empat kuadran (4Q) baharu yang saling melengkapi menggunakan kawasan linear dan tepu MOSFET (Metal Oxide Semiconductor Field Effect Transistor) dicadangkan untuk julat dinamik yang luas dan fleksibiliti unggul julat input. Pengganda ini beroperasi di rantau ini kecuali untuk voltan ambang VT kepada sifar. Kesahan litar yang dicadangkan disahkan melalui simulasi HSPICE.
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Salinan
Tsutomu SUZUKI, Takao OURA, Teru YONEYAMA, Hideki ASAI, "Design and Simulation of 4Q-Multiplier Using Linear and Saturation Regions of MOSFET Complementally" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 6, pp. 1242-1248, June 2002, doi: .
Abstract: A new four-quadrant (4Q) Multiplier complementally using linear and saturation regions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is proposed for the wide dynamic range and superior flexibility of the input range. This multiplier operates in the region except for the threshold voltage VT to zero. The validity of the proposed circuit is confirmed through HSPICE simulation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_6_1242/_p
Salinan
@ARTICLE{e85-a_6_1242,
author={Tsutomu SUZUKI, Takao OURA, Teru YONEYAMA, Hideki ASAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design and Simulation of 4Q-Multiplier Using Linear and Saturation Regions of MOSFET Complementally},
year={2002},
volume={E85-A},
number={6},
pages={1242-1248},
abstract={A new four-quadrant (4Q) Multiplier complementally using linear and saturation regions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is proposed for the wide dynamic range and superior flexibility of the input range. This multiplier operates in the region except for the threshold voltage VT to zero. The validity of the proposed circuit is confirmed through HSPICE simulation.},
keywords={},
doi={},
ISSN={},
month={June},}
Salinan
TY - JOUR
TI - Design and Simulation of 4Q-Multiplier Using Linear and Saturation Regions of MOSFET Complementally
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1242
EP - 1248
AU - Tsutomu SUZUKI
AU - Takao OURA
AU - Teru YONEYAMA
AU - Hideki ASAI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2002
AB - A new four-quadrant (4Q) Multiplier complementally using linear and saturation regions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is proposed for the wide dynamic range and superior flexibility of the input range. This multiplier operates in the region except for the threshold voltage VT to zero. The validity of the proposed circuit is confirmed through HSPICE simulation.
ER -