The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini membentangkan kaedah pengoptimuman kod berorientasikan DSP baharu untuk meningkatkan prestasi dengan mengeksploitasi ciri seni bina khusus pemproses isyarat digital. Dalam kaedah yang dicadangkan, kod sumber diterjemahkan ke dalam borang tugasan tunggal statik sambil mengekalkan maklumat peringkat tinggi yang berkaitan dengan gelung dan pengiraan alamat akses tatasusunan. Maklumat ini digunakan dalam menjana arahan gelung perkakasan dan arahan selari yang disediakan oleh kebanyakan pemproses isyarat digital. Selain graf aliran data kawalan konvensional, graf baharu digunakan untuk memudahkan pencarian mod pengalamatan pengubahsuaian automatik dengan cekap. Keputusan eksperimen pada program penanda aras menunjukkan bahawa kaedah yang dicadangkan adalah berkesan dalam meningkatkan prestasi.
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Salinan
Jong-Yeol LEE, In-Cheol PARK, "Loop and Address Code Optimization for Digital Signal Processors" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 6, pp. 1408-1415, June 2002, doi: .
Abstract: This paper presents a new DSP-oriented code optimization method to enhance performance by exploiting the specific architectural features of digital signal processors. In the proposed method, a source code is translated into the static single assignment form while preserving the high-level information related to loops and the address computation of array accesses. The information is used in generating hardware loop instructions and parallel instructions provided by most digital signal processors. In addition to the conventional control-data flow graph, a new graph is employed to make it easy to find auto-modification addressing modes efficiently. Experimental results on benchmark programs show that the proposed method is effective in improving performance.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_6_1408/_p
Salinan
@ARTICLE{e85-a_6_1408,
author={Jong-Yeol LEE, In-Cheol PARK, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Loop and Address Code Optimization for Digital Signal Processors},
year={2002},
volume={E85-A},
number={6},
pages={1408-1415},
abstract={This paper presents a new DSP-oriented code optimization method to enhance performance by exploiting the specific architectural features of digital signal processors. In the proposed method, a source code is translated into the static single assignment form while preserving the high-level information related to loops and the address computation of array accesses. The information is used in generating hardware loop instructions and parallel instructions provided by most digital signal processors. In addition to the conventional control-data flow graph, a new graph is employed to make it easy to find auto-modification addressing modes efficiently. Experimental results on benchmark programs show that the proposed method is effective in improving performance.},
keywords={},
doi={},
ISSN={},
month={June},}
Salinan
TY - JOUR
TI - Loop and Address Code Optimization for Digital Signal Processors
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1408
EP - 1415
AU - Jong-Yeol LEE
AU - In-Cheol PARK
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2002
AB - This paper presents a new DSP-oriented code optimization method to enhance performance by exploiting the specific architectural features of digital signal processors. In the proposed method, a source code is translated into the static single assignment form while preserving the high-level information related to loops and the address computation of array accesses. The information is used in generating hardware loop instructions and parallel instructions provided by most digital signal processors. In addition to the conventional control-data flow graph, a new graph is employed to make it easy to find auto-modification addressing modes efficiently. Experimental results on benchmark programs show that the proposed method is effective in improving performance.
ER -