The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Pengesanan talian adalah teknik pemprosesan imej asas yang mempunyai pelbagai aplikasi dalam bidang penglihatan komputer. Sebagai contoh, penjagaan lorong yang diperlukan untuk merealisasikan kenderaan autonomi boleh dilaksanakan berdasarkan teknik pengesanan talian. Walau bagaimanapun, untuk tujuan sedemikian, kependaman pengesanan rendah dan penggunaan kuasa adalah penting. Menggunakan pemprosesan strim berasaskan perkakasan dianggap sebagai cara yang berkesan untuk mencapai sifat sedemikian kerana ia menghapuskan keperluan untuk menyimpan keseluruhan bingkai ke dalam memori luaran yang memakan tenaga. Di samping itu, menerima pakai FPGA membolehkan kami mengekalkan fleksibiliti pemprosesan perisian. Pengesan segmen garisan (LSD) ialah algoritma berdasarkan kecerunan intensiti, dan berprestasi lebih baik daripada transformasi Hough yang terkenal dari segi kelajuan dan ketepatan pemprosesan. Walau bagaimanapun, melaksanakan LSD asal pada FPGA sebagai struktur saluran paip adalah sukar terutamanya kerana pendekatan pertumbuhan wilayah berulangnya. Oleh itu, kami mencadangkan algoritma pengesanan segmen garisan yang mudah dan mesra strim berdasarkan konsep LSD. Keseluruhan sistem dilaksanakan pada Xilinx Zynq-7000 XC7Z020-1CLG400C FPGA tanpa sebarang memori luaran. Keputusan penilaian mendedahkan bahawa sistem yang dilaksanakan mampu mengesan segmen talian dengan jayanya dan padat dengan 7.5% RAM Blok dan kurang daripada 7.0% daripada sumber lain yang digunakan, sambil mengekalkan daya pemprosesan 60 fps untuk video VGA. Ia juga menunjukkan bahawa sistem ini adalah cekap kuasa berbanding pemprosesan perisian pada CPU.
Taito MANABE
Nagasaki University
Taichi KATAYAMA
Nagasaki University
Yuichiro SHIBATA
Nagasaki University
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Salinan
Taito MANABE, Taichi KATAYAMA, Yuichiro SHIBATA, "FPGA Implementation of a Stream-Based Real-Time Hardware Line Segment Detector" in IEICE TRANSACTIONS on Fundamentals,
vol. E105-A, no. 3, pp. 468-477, March 2022, doi: 10.1587/transfun.2021VLP0009.
Abstract: Line detection is the fundamental image processing technique which has various applications in the field of computer vision. For example, lane keeping required to realize autonomous vehicles can be implemented based on line detection technique. For such purposes, however, low detection latency and power consumption are essential. Using hardware-based stream processing is considered as an effective way to achieve such properties since it eliminates the need of storing the whole frame into energy-consuming external memory. In addition, adopting FPGAs enables us to keep flexibility of software processing. The line segment detector (LSD) is the algorithm based on intensity gradient, and performs better than the well-known Hough transform in terms of processing speed and accuracy. However, implementing the original LSD on FPGAs as a pipeline structure is difficult mainly because of its iterative region growing approach. Therefore, we propose a simple and stream-friendly line segment detection algorithm based on the concept of LSD. The whole system is implemented on a Xilinx Zynq-7000 XC7Z020-1CLG400C FPGA without any external memory. Evaluation results reveal that the implemented system is able to detect line segments successfully and is compact with 7.5% of Block RAM and less than 7.0% of the other resources used, while maintaining 60 fps throughput for VGA videos. It is also shown that the system is power-efficient compared to software processing on CPUs.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2021VLP0009/_p
Salinan
@ARTICLE{e105-a_3_468,
author={Taito MANABE, Taichi KATAYAMA, Yuichiro SHIBATA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={FPGA Implementation of a Stream-Based Real-Time Hardware Line Segment Detector},
year={2022},
volume={E105-A},
number={3},
pages={468-477},
abstract={Line detection is the fundamental image processing technique which has various applications in the field of computer vision. For example, lane keeping required to realize autonomous vehicles can be implemented based on line detection technique. For such purposes, however, low detection latency and power consumption are essential. Using hardware-based stream processing is considered as an effective way to achieve such properties since it eliminates the need of storing the whole frame into energy-consuming external memory. In addition, adopting FPGAs enables us to keep flexibility of software processing. The line segment detector (LSD) is the algorithm based on intensity gradient, and performs better than the well-known Hough transform in terms of processing speed and accuracy. However, implementing the original LSD on FPGAs as a pipeline structure is difficult mainly because of its iterative region growing approach. Therefore, we propose a simple and stream-friendly line segment detection algorithm based on the concept of LSD. The whole system is implemented on a Xilinx Zynq-7000 XC7Z020-1CLG400C FPGA without any external memory. Evaluation results reveal that the implemented system is able to detect line segments successfully and is compact with 7.5% of Block RAM and less than 7.0% of the other resources used, while maintaining 60 fps throughput for VGA videos. It is also shown that the system is power-efficient compared to software processing on CPUs.},
keywords={},
doi={10.1587/transfun.2021VLP0009},
ISSN={1745-1337},
month={March},}
Salinan
TY - JOUR
TI - FPGA Implementation of a Stream-Based Real-Time Hardware Line Segment Detector
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 468
EP - 477
AU - Taito MANABE
AU - Taichi KATAYAMA
AU - Yuichiro SHIBATA
PY - 2022
DO - 10.1587/transfun.2021VLP0009
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E105-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2022
AB - Line detection is the fundamental image processing technique which has various applications in the field of computer vision. For example, lane keeping required to realize autonomous vehicles can be implemented based on line detection technique. For such purposes, however, low detection latency and power consumption are essential. Using hardware-based stream processing is considered as an effective way to achieve such properties since it eliminates the need of storing the whole frame into energy-consuming external memory. In addition, adopting FPGAs enables us to keep flexibility of software processing. The line segment detector (LSD) is the algorithm based on intensity gradient, and performs better than the well-known Hough transform in terms of processing speed and accuracy. However, implementing the original LSD on FPGAs as a pipeline structure is difficult mainly because of its iterative region growing approach. Therefore, we propose a simple and stream-friendly line segment detection algorithm based on the concept of LSD. The whole system is implemented on a Xilinx Zynq-7000 XC7Z020-1CLG400C FPGA without any external memory. Evaluation results reveal that the implemented system is able to detect line segments successfully and is compact with 7.5% of Block RAM and less than 7.0% of the other resources used, while maintaining 60 fps throughput for VGA videos. It is also shown that the system is power-efficient compared to software processing on CPUs.
ER -