The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Pengesanan objek visual pada sistem terbenam melibatkan masalah pengoptimuman berbilang objektif dengan adanya pertukaran antara penggunaan kuasa, prestasi pemprosesan dan ketepatan pengesanan. Untuk penyelesaian Pareto baharu dengan prestasi pemprosesan tinggi dan penggunaan kuasa yang rendah, kertas kerja ini mencadangkan seni bina perkakasan untuk ensemble pokok keputusan menggunakan berbilang saluran ciri. Untuk pengesanan yang cekap, seni bina yang dicadangkan menggunakan dimensi saluran ciri sebagai tambahan kepada keselarian dalam ruang imej dan mengguna pakai penjadualan tugas untuk mencapai akses memori rawak tanpa konflik. Keputusan penilaian menunjukkan bahawa pelaksanaan FPGA bagi seni bina yang dicadangkan dengan ciri saluran agregat pengesan pejalan kaki boleh memproses 229 juta sampel sesaat pada frekuensi operasi 100MHz sementara memerlukan jumlah sumber yang agak kecil. Akibatnya, seni bina yang dicadangkan mencapai prestasi pemprosesan 350fps untuk imej HD Penuh 1080P dan mengatasi prestasi seni bina perkakasan pengesanan objek konvensional yang dibangunkan untuk sistem terbenam.
Koichi MITSUNARI
Osaka University
Jaehoon YU
Osaka University
Takao ONOYE
Osaka University
Masanori HASHIMOTO
Osaka University
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Salinan
Koichi MITSUNARI, Jaehoon YU, Takao ONOYE, Masanori HASHIMOTO, "Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble" in IEICE TRANSACTIONS on Fundamentals,
vol. E101-A, no. 9, pp. 1298-1307, September 2018, doi: 10.1587/transfun.E101.A.1298.
Abstract: Visual object detection on embedded systems involves a multi-objective optimization problem in the presence of trade-offs between power consumption, processing performance, and detection accuracy. For a new Pareto solution with high processing performance and low power consumption, this paper proposes a hardware architecture for decision tree ensemble using multiple channels of features. For efficient detection, the proposed architecture utilizes the dimensionality of feature channels in addition to parallelism in image space and adopts task scheduling to attain random memory access without conflict. Evaluation results show that an FPGA implementation of the proposed architecture with an aggregated channel features pedestrian detector can process 229 million samples per second at 100MHz operation frequency while it requires a relatively small amount of resources. Consequently, the proposed architecture achieves 350fps processing performance for 1080P Full HD images and outperforms conventional object detection hardware architectures developed for embedded systems.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.1298/_p
Salinan
@ARTICLE{e101-a_9_1298,
author={Koichi MITSUNARI, Jaehoon YU, Takao ONOYE, Masanori HASHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble},
year={2018},
volume={E101-A},
number={9},
pages={1298-1307},
abstract={Visual object detection on embedded systems involves a multi-objective optimization problem in the presence of trade-offs between power consumption, processing performance, and detection accuracy. For a new Pareto solution with high processing performance and low power consumption, this paper proposes a hardware architecture for decision tree ensemble using multiple channels of features. For efficient detection, the proposed architecture utilizes the dimensionality of feature channels in addition to parallelism in image space and adopts task scheduling to attain random memory access without conflict. Evaluation results show that an FPGA implementation of the proposed architecture with an aggregated channel features pedestrian detector can process 229 million samples per second at 100MHz operation frequency while it requires a relatively small amount of resources. Consequently, the proposed architecture achieves 350fps processing performance for 1080P Full HD images and outperforms conventional object detection hardware architectures developed for embedded systems.},
keywords={},
doi={10.1587/transfun.E101.A.1298},
ISSN={1745-1337},
month={September},}
Salinan
TY - JOUR
TI - Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1298
EP - 1307
AU - Koichi MITSUNARI
AU - Jaehoon YU
AU - Takao ONOYE
AU - Masanori HASHIMOTO
PY - 2018
DO - 10.1587/transfun.E101.A.1298
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E101-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2018
AB - Visual object detection on embedded systems involves a multi-objective optimization problem in the presence of trade-offs between power consumption, processing performance, and detection accuracy. For a new Pareto solution with high processing performance and low power consumption, this paper proposes a hardware architecture for decision tree ensemble using multiple channels of features. For efficient detection, the proposed architecture utilizes the dimensionality of feature channels in addition to parallelism in image space and adopts task scheduling to attain random memory access without conflict. Evaluation results show that an FPGA implementation of the proposed architecture with an aggregated channel features pedestrian detector can process 229 million samples per second at 100MHz operation frequency while it requires a relatively small amount of resources. Consequently, the proposed architecture achieves 350fps processing performance for 1080P Full HD images and outperforms conventional object detection hardware architectures developed for embedded systems.
ER -