The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Apabila teknologi pembuatan peranti semikonduktor berkembang ke arah penyepaduan yang lebih tinggi dan saiz ciri yang dikurangkan, jurang antara tahap kecacatan yang dianggarkan pada peringkat reka bentuk dan yang dilaporkan untuk peranti fabrikasi telah menjadi lebih luas, menjadikannya lebih sukar untuk mengawal jumlah kos pembuatan termasuk kos ujian dan kos untuk kegagalan medan. Untuk menganggarkan liputan kerosakan dengan lebih tepat mempertimbangkan kebarangkalian berlakunya kerosakan, kami telah mencadangkan anggaran liputan kesalahan berwajaran berdasarkan kawasan kritikal yang sepadan dengan setiap kerosakan. Model kerosakan yang berbeza sebelum ini dikendalikan secara berasingan; oleh itu, kecekapan mampatan corak dan masa jalan tidak dioptimumkan. Dalam kajian ini, kami mencadangkan skim penjanaan corak ujian pantas yang mempertimbangkan jambatan berwajaran dan liputan kerosakan terbuka secara bersepadu. Skim yang dicadangkan menggunakan penjanaan corak ujian dua langkah, di mana corak ujian yang dijana pada langkah kedua yang menyasarkan hanya kerosakan jambatan disusun semula dengan tetingkap carian saiz tetap, mencapai O(n) kerumitan pengiraan. Keputusan eksperimen menunjukkan bahawa dengan 10% daripada saiz kesalahan sasaran awal dan saiz tetingkap kecil yang tetap, skim yang dicadangkan mencapai kira-kira 100 kali pengurangan masa jalan jika dibandingkan dengan penyusunan semula berasaskan tamak yang mudah, sebagai pertukaran kira-kira 5% pertambahan kiraan corak.
Masayuki ARAI
Nihon University
Shingo INUYAMA
Tokyo Metropolitan University
Kazuhiko IWASAKI
Tokyo Metropolitan University
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Salinan
Masayuki ARAI, Shingo INUYAMA, Kazuhiko IWASAKI, "Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering" in IEICE TRANSACTIONS on Fundamentals,
vol. E101-A, no. 12, pp. 2262-2270, December 2018, doi: 10.1587/transfun.E101.A.2262.
Abstract: As semiconductor device manufacturing technology evolves toward higher integration and reduced feature size, the gap between the defect level estimated at the design stage and that reported for fabricated devices has become wider, making it more difficult to control total manufacturing cost including test cost and cost for field failure. To estimate fault coverage more precisely considering occurrence probabilities of faults, we have proposed weighted fault coverage estimation based on critical area corresponding to each fault. Previously different fault models were handled separately; thus, pattern compression efficiency and runtime were not optimized. In this study, we propose a fast test pattern generation scheme that considers weighted bridge and open fault coverage in an integrated manner. The proposed scheme applies two-step test pattern generation, wherein test patterns generated at second step that target only bridge faults are reordered with a search window of fixed size, achieving O(n) computational complexity. Experimental results indicate that with 10% of the initial target fault size and a fixed, small window size, the proposed scheme achieves approximately 100 times runtime reduction when compared to simple greedy-based reordering, in exchange for about 5% pattern count increment.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.2262/_p
Salinan
@ARTICLE{e101-a_12_2262,
author={Masayuki ARAI, Shingo INUYAMA, Kazuhiko IWASAKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering},
year={2018},
volume={E101-A},
number={12},
pages={2262-2270},
abstract={As semiconductor device manufacturing technology evolves toward higher integration and reduced feature size, the gap between the defect level estimated at the design stage and that reported for fabricated devices has become wider, making it more difficult to control total manufacturing cost including test cost and cost for field failure. To estimate fault coverage more precisely considering occurrence probabilities of faults, we have proposed weighted fault coverage estimation based on critical area corresponding to each fault. Previously different fault models were handled separately; thus, pattern compression efficiency and runtime were not optimized. In this study, we propose a fast test pattern generation scheme that considers weighted bridge and open fault coverage in an integrated manner. The proposed scheme applies two-step test pattern generation, wherein test patterns generated at second step that target only bridge faults are reordered with a search window of fixed size, achieving O(n) computational complexity. Experimental results indicate that with 10% of the initial target fault size and a fixed, small window size, the proposed scheme achieves approximately 100 times runtime reduction when compared to simple greedy-based reordering, in exchange for about 5% pattern count increment.},
keywords={},
doi={10.1587/transfun.E101.A.2262},
ISSN={1745-1337},
month={December},}
Salinan
TY - JOUR
TI - Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2262
EP - 2270
AU - Masayuki ARAI
AU - Shingo INUYAMA
AU - Kazuhiko IWASAKI
PY - 2018
DO - 10.1587/transfun.E101.A.2262
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E101-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2018
AB - As semiconductor device manufacturing technology evolves toward higher integration and reduced feature size, the gap between the defect level estimated at the design stage and that reported for fabricated devices has become wider, making it more difficult to control total manufacturing cost including test cost and cost for field failure. To estimate fault coverage more precisely considering occurrence probabilities of faults, we have proposed weighted fault coverage estimation based on critical area corresponding to each fault. Previously different fault models were handled separately; thus, pattern compression efficiency and runtime were not optimized. In this study, we propose a fast test pattern generation scheme that considers weighted bridge and open fault coverage in an integrated manner. The proposed scheme applies two-step test pattern generation, wherein test patterns generated at second step that target only bridge faults are reordered with a search window of fixed size, achieving O(n) computational complexity. Experimental results indicate that with 10% of the initial target fault size and a fixed, small window size, the proposed scheme achieves approximately 100 times runtime reduction when compared to simple greedy-based reordering, in exchange for about 5% pattern count increment.
ER -