The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dalam kertas kerja ini, untuk memudahkan reka bentuk litar tak segerak, kami mencadangkan kaedah penukaran daripada model Tahap Pemindahan Daftar (RTL) segerak kepada model RTL tak segerak dengan pelaksanaan data berpakatan. Kaedah yang dicadangkan terdiri daripada penjanaan perwakilan perantaraan daripada model RTL segerak yang diberikan dan penjanaan model RTL tak segerak daripada perwakilan perantaraan. Ini membolehkan kami menangani gaya perwakilan yang berbeza bagi model RTL segerak. Kami menggunakan Bahasa Penanda eXtensible (XML) sebagai perwakilan perantaraan. Selain model RTL tak segerak, kaedah yang dicadangkan menjana model simulasi apabila pelaksanaan sasaran ialah Tatasusunan Gerbang Boleh Aturcara Medan dan satu set kekangan bukan pengoptimuman untuk litar kawalan yang digunakan dalam sintesis logik dan sintesis susun atur. Dalam percubaan, kami menunjukkan bahawa kaedah yang dicadangkan boleh menukar model RTL segerak yang ditentukan secara manual dan diperolehi oleh alat sintesis peringkat tinggi kepada yang tidak segerak.
Shogo SEMBA
the University of Aizu
Hiroshi SAITO
the University of Aizu
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Salinan
Shogo SEMBA, Hiroshi SAITO, "Conversion from Synchronous RTL Models to Asynchronous RTL Models" in IEICE TRANSACTIONS on Fundamentals,
vol. E102-A, no. 7, pp. 904-913, July 2019, doi: 10.1587/transfun.E102.A.904.
Abstract: In this paper, to make asynchronous circuit design easy, we propose a conversion method from synchronous Register Transfer Level (RTL) models to asynchronous RTL models with bundled-data implementation. The proposed method consists of the generation of an intermediate representation from a given synchronous RTL model and the generation of an asynchronous RTL model from the intermediate representation. This allows us to deal with different representation styles of synchronous RTL models. We use the eXtensible Markup Language (XML) as the intermediate representation. In addition to the asynchronous RTL model, the proposed method generates a simulation model when the target implementation is a Field Programmable Gate Array and a set of non-optimization constraints for the control circuit used in logic synthesis and layout synthesis. In the experiment, we demonstrate that the proposed method can convert synchronous RTL models specified manually and obtained by a high-level synthesis tool to asynchronous ones.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.904/_p
Salinan
@ARTICLE{e102-a_7_904,
author={Shogo SEMBA, Hiroshi SAITO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Conversion from Synchronous RTL Models to Asynchronous RTL Models},
year={2019},
volume={E102-A},
number={7},
pages={904-913},
abstract={In this paper, to make asynchronous circuit design easy, we propose a conversion method from synchronous Register Transfer Level (RTL) models to asynchronous RTL models with bundled-data implementation. The proposed method consists of the generation of an intermediate representation from a given synchronous RTL model and the generation of an asynchronous RTL model from the intermediate representation. This allows us to deal with different representation styles of synchronous RTL models. We use the eXtensible Markup Language (XML) as the intermediate representation. In addition to the asynchronous RTL model, the proposed method generates a simulation model when the target implementation is a Field Programmable Gate Array and a set of non-optimization constraints for the control circuit used in logic synthesis and layout synthesis. In the experiment, we demonstrate that the proposed method can convert synchronous RTL models specified manually and obtained by a high-level synthesis tool to asynchronous ones.},
keywords={},
doi={10.1587/transfun.E102.A.904},
ISSN={1745-1337},
month={July},}
Salinan
TY - JOUR
TI - Conversion from Synchronous RTL Models to Asynchronous RTL Models
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 904
EP - 913
AU - Shogo SEMBA
AU - Hiroshi SAITO
PY - 2019
DO - 10.1587/transfun.E102.A.904
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2019
AB - In this paper, to make asynchronous circuit design easy, we propose a conversion method from synchronous Register Transfer Level (RTL) models to asynchronous RTL models with bundled-data implementation. The proposed method consists of the generation of an intermediate representation from a given synchronous RTL model and the generation of an asynchronous RTL model from the intermediate representation. This allows us to deal with different representation styles of synchronous RTL models. We use the eXtensible Markup Language (XML) as the intermediate representation. In addition to the asynchronous RTL model, the proposed method generates a simulation model when the target implementation is a Field Programmable Gate Array and a set of non-optimization constraints for the control circuit used in logic synthesis and layout synthesis. In the experiment, we demonstrate that the proposed method can convert synchronous RTL models specified manually and obtained by a high-level synthesis tool to asynchronous ones.
ER -