The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
VLSI yang melakukan pemprosesan isyarat berhampiran penderia inframerah yang disejukkan kepada suhu ultra-rendah diperlukan. Ujian kelewatan cip tersebut mesti dilaksanakan pada suhu ultra-rendah manakala ujian kefungsian boleh dilakukan pada suhu bilik selagi ralat pemasaan penahanan tidak berlaku. Dalam surat ini, kami menumpukan pada pelanggaran masa penahanan dan menilai kebolehlaksanaan ujian kefungsian litar suhu ultra-rendah pada suhu bilik. Penilaian eksperimen dengan kajian kes menunjukkan bahawa ujian berfungsi pada suhu bilik adalah mungkin.
Takahiro NAKAYAMA
Osaka University
Masanori HASHIMOTO
Osaka University
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Salinan
Takahiro NAKAYAMA, Masanori HASHIMOTO, "Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature" in IEICE TRANSACTIONS on Fundamentals,
vol. E102-A, no. 7, pp. 914-917, July 2019, doi: 10.1587/transfun.E102.A.914.
Abstract: VLSIs that perform signal processing near infrared sensors cooled to ultra-low temperature are demanded. Delay test of those chips must be executed at ultra-low temperature while functional test could be performed at room temperature as long as hold timing errors do not occur. In this letter, we focus on the hold timing violation and evaluate the feasibility of functional test of ultra-low temperature circuits at room temperature. Experimental evaluation with a case study shows that the functional test at room temperature is possible.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.914/_p
Salinan
@ARTICLE{e102-a_7_914,
author={Takahiro NAKAYAMA, Masanori HASHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature},
year={2019},
volume={E102-A},
number={7},
pages={914-917},
abstract={VLSIs that perform signal processing near infrared sensors cooled to ultra-low temperature are demanded. Delay test of those chips must be executed at ultra-low temperature while functional test could be performed at room temperature as long as hold timing errors do not occur. In this letter, we focus on the hold timing violation and evaluate the feasibility of functional test of ultra-low temperature circuits at room temperature. Experimental evaluation with a case study shows that the functional test at room temperature is possible.},
keywords={},
doi={10.1587/transfun.E102.A.914},
ISSN={1745-1337},
month={July},}
Salinan
TY - JOUR
TI - Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 914
EP - 917
AU - Takahiro NAKAYAMA
AU - Masanori HASHIMOTO
PY - 2019
DO - 10.1587/transfun.E102.A.914
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2019
AB - VLSIs that perform signal processing near infrared sensors cooled to ultra-low temperature are demanded. Delay test of those chips must be executed at ultra-low temperature while functional test could be performed at room temperature as long as hold timing errors do not occur. In this letter, we focus on the hold timing violation and evaluate the feasibility of functional test of ultra-low temperature circuits at room temperature. Experimental evaluation with a case study shows that the functional test at room temperature is possible.
ER -