The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Untuk VLSI teknologi nanometer terkini dan akan datang, variasi kelewatan statik dan dinamik menjadi masalah yang serius. Dalam kebanyakan kes, kekangan penahanan, serta kekangan persediaan, menjadi kritikal untuk mengunci isyarat yang betul di bawah variasi kelewatan. Kertas kerja ini menangani kekangan penahanan dalam litar laluan data, dan membincangkan tugasan daftar dalam sintesis tahap tinggi dengan mengambil kira variasi kelewatan. Pendekatan kami untuk memastikan kekangan penahanan di bawah variasi kelewatan adalah untuk membesarkan kelewatan laluan minimum antara daftar, yang dipanggil pampasan kelewatan laluan minimum (MDC) dalam kertas ini. MDC boleh dilakukan dengan memasukkan elemen kelewatan terutamanya dalam laluan bukan kritikal unit berfungsi (FU). Salah satu sumbangan kami adalah untuk menunjukkan bahawa pengecilan bilangan FU pampasan kelewatan laluan minimum adalah NP-keras secara umum, dan ia berada dalam kelas P jika bilangan FU adalah pemalar. Algoritma masa polinomial untuk yang terakhir juga ditunjukkan dalam kertas ini. Selain itu, rumusan pengaturcaraan linear integer (ILP) turut dipersembahkan. Kaedah yang dicadangkan menjana laluan data yang mempunyai (1) keteguhan terhadap variasi kelewatan, yang dipastikan sebahagiannya oleh teknik MDC dan sebahagian lagi oleh penetapan daftar berasaskan SRV, dan (2) bilangan minimum MDC dan daftar yang mungkin.
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Salinan
Keisuke INOUE, Mineo KANEKO, Tsuyoshi IWAGAKI, "Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 4, pp. 1096-1105, April 2009, doi: 10.1587/transfun.E92.A.1096.
Abstract: For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. This paper treats the hold constraint in a datapath circuit, and discusses a register assignment in high level synthesis considering delay variations. Our approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path delay compensation (MDC) in this paper. MDC can be done by inserting delay elements mainly in non-critical paths of a functional unit (FU). One of our contributions is to show that the minimization of the number of minimum-path delay compensated FUs is NP-hard in general, and it is in the class P if the number of FUs is a constant. A polynomial time algorithm for the latter is also shown in this paper. In addition, an integer linear programming (ILP) formulation is also presented. The proposed method generates a datapath having (1) robustness against delay variations, which is ensured partly by MDC technique and partly by SRV-based register assignment, and (2) the minimum possible numbers of MDCs and registers.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.1096/_p
Salinan
@ARTICLE{e92-a_4_1096,
author={Keisuke INOUE, Mineo KANEKO, Tsuyoshi IWAGAKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths},
year={2009},
volume={E92-A},
number={4},
pages={1096-1105},
abstract={For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. This paper treats the hold constraint in a datapath circuit, and discusses a register assignment in high level synthesis considering delay variations. Our approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path delay compensation (MDC) in this paper. MDC can be done by inserting delay elements mainly in non-critical paths of a functional unit (FU). One of our contributions is to show that the minimization of the number of minimum-path delay compensated FUs is NP-hard in general, and it is in the class P if the number of FUs is a constant. A polynomial time algorithm for the latter is also shown in this paper. In addition, an integer linear programming (ILP) formulation is also presented. The proposed method generates a datapath having (1) robustness against delay variations, which is ensured partly by MDC technique and partly by SRV-based register assignment, and (2) the minimum possible numbers of MDCs and registers.},
keywords={},
doi={10.1587/transfun.E92.A.1096},
ISSN={1745-1337},
month={April},}
Salinan
TY - JOUR
TI - Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1096
EP - 1105
AU - Keisuke INOUE
AU - Mineo KANEKO
AU - Tsuyoshi IWAGAKI
PY - 2009
DO - 10.1587/transfun.E92.A.1096
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2009
AB - For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. This paper treats the hold constraint in a datapath circuit, and discusses a register assignment in high level synthesis considering delay variations. Our approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path delay compensation (MDC) in this paper. MDC can be done by inserting delay elements mainly in non-critical paths of a functional unit (FU). One of our contributions is to show that the minimization of the number of minimum-path delay compensated FUs is NP-hard in general, and it is in the class P if the number of FUs is a constant. A polynomial time algorithm for the latter is also shown in this paper. In addition, an integer linear programming (ILP) formulation is also presented. The proposed method generates a datapath having (1) robustness against delay variations, which is ensured partly by MDC technique and partly by SRV-based register assignment, and (2) the minimum possible numbers of MDCs and registers.
ER -