The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Kertas kerja ini mencadangkan rangka kerja DVC selari yang merawat setiap bitplane secara bebas untuk mengurangkan masa penyahkodan. Malangnya, penyejajaran mudah menjana kebarangkalian bit yang tidak tepat kerana maklumat sampingan tambahan tidak tersedia untuk penyahkodan bitplanes berikutnya, yang merendahkan kecekapan pengekodan. Penyelesaian kami ialah kaedah anggaran yang berkesan yang boleh mengira kebarangkalian bit setepat mungkin dengan penetapan indeks tanpa menggunakan maklumat sampingan. Selain itu, kami meningkatkan prestasi pengekodan LDPC Suai Kadar (RA-LDPC), yang digunakan dalam rangka kerja DVC selari. Cadangan ini memilih matriks jarang yang sesuai untuk setiap bitplane mengikut keputusan anggaran kadar sindrom di bahagian pengekod. Simulasi menunjukkan bahawa kaedah selari kami mengurangkan masa penyahkodan sehingga 35[%] dan mencapai pengurangan kadar bit kira-kira 10[%].
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Salinan
Yoshihide TONOMURA, Takayuki NAKACHI, Tatsuya FUJII, Hitoshi KIYA, "Parallel Processing of Distributed Video Coding to Reduce Decoding Time" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 10, pp. 2463-2470, October 2009, doi: 10.1587/transfun.E92.A.2463.
Abstract: This paper proposes a parallelized DVC framework that treats each bitplane independently to reduce the decoding time. Unfortunately, simple parallelization generates inaccurate bit probabilities because additional side information is not available for the decoding of subsequent bitplanes, which degrades encoding efficiency. Our solution is an effective estimation method that can calculate the bit probability as accurately as possible by index assignment without recourse to side information. Moreover, we improve the coding performance of Rate-Adaptive LDPC (RA-LDPC), which is used in the parallelized DVC framework. This proposal selects a fitting sparse matrix for each bitplane according to the syndrome rate estimation results at the encoder side. Simulations show that our parallelization method reduces the decoding time by up to 35[%] and achieves a bit rate reduction of about 10[%].
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.2463/_p
Salinan
@ARTICLE{e92-a_10_2463,
author={Yoshihide TONOMURA, Takayuki NAKACHI, Tatsuya FUJII, Hitoshi KIYA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Parallel Processing of Distributed Video Coding to Reduce Decoding Time},
year={2009},
volume={E92-A},
number={10},
pages={2463-2470},
abstract={This paper proposes a parallelized DVC framework that treats each bitplane independently to reduce the decoding time. Unfortunately, simple parallelization generates inaccurate bit probabilities because additional side information is not available for the decoding of subsequent bitplanes, which degrades encoding efficiency. Our solution is an effective estimation method that can calculate the bit probability as accurately as possible by index assignment without recourse to side information. Moreover, we improve the coding performance of Rate-Adaptive LDPC (RA-LDPC), which is used in the parallelized DVC framework. This proposal selects a fitting sparse matrix for each bitplane according to the syndrome rate estimation results at the encoder side. Simulations show that our parallelization method reduces the decoding time by up to 35[%] and achieves a bit rate reduction of about 10[%].},
keywords={},
doi={10.1587/transfun.E92.A.2463},
ISSN={1745-1337},
month={October},}
Salinan
TY - JOUR
TI - Parallel Processing of Distributed Video Coding to Reduce Decoding Time
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2463
EP - 2470
AU - Yoshihide TONOMURA
AU - Takayuki NAKACHI
AU - Tatsuya FUJII
AU - Hitoshi KIYA
PY - 2009
DO - 10.1587/transfun.E92.A.2463
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 2009
AB - This paper proposes a parallelized DVC framework that treats each bitplane independently to reduce the decoding time. Unfortunately, simple parallelization generates inaccurate bit probabilities because additional side information is not available for the decoding of subsequent bitplanes, which degrades encoding efficiency. Our solution is an effective estimation method that can calculate the bit probability as accurately as possible by index assignment without recourse to side information. Moreover, we improve the coding performance of Rate-Adaptive LDPC (RA-LDPC), which is used in the parallelized DVC framework. This proposal selects a fitting sparse matrix for each bitplane according to the syndrome rate estimation results at the encoder side. Simulations show that our parallelization method reduces the decoding time by up to 35[%] and achieves a bit rate reduction of about 10[%].
ER -