The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Memandangkan teknologi litar bersepadu telah melalui penskalaan bawah berterusan untuk meningkatkan prestasi LSI dan mengurangkan saiz cip, reka bentuk untuk kebolehkilangan (DFM) dan reka bentuk untuk hasil (DFY) telah menjadi sangat penting. Sebagai salah satu kaedah DFM/DFY, teknik pemasukan yang berlebihan menggunakan seberapa banyak vias yang mungkin untuk menyambung wayar logam antara lapisan yang berbeza. Dalam kertas kerja ini, kami menumpukan pada vias berlebihan dan mencadangkan lebihan yang berkesan melalui kaedah sisipan untuk kegunaan praktikal untuk menangani kebimbangan kebolehubahan pembuatan dan kebolehpercayaan. Pertama, keputusan analisis statistik untuk melalui rintangan dan melalui kapasitansi dalam beberapa susun atur fizikal sebenar ditunjukkan, dan kesan ke atas kelewatan litar variasi rintangan vias yang disebabkan oleh kebolehubahan pembuatan dijelaskan. Kemudian, fungsi penilaian variasi kelewatan, migrasi elektro (EM) dan migrasi tegasan (SM) ditakrifkan dan kaedah praktikal mengenai lebihan melalui sisipan dicadangkan. Keputusan eksperimen menunjukkan bahawa LSI dengan vias berlebihan yang dimasukkan oleh kaedah kami teguh terhadap masalah kebolehubahan dan kebolehpercayaan pembuatan.
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Salinan
Yuji TAKASHIMA, Kazuyuki OOYA, Atsushi KUROKAWA, "Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 12, pp. 2962-2970, December 2009, doi: 10.1587/transfun.E92.A.2962.
Abstract: As the integrated circuit technology has undergone continuous downscaling to improve the LSI performance and reduce chip size, design for manufacturability (DFM) and design for yield (DFY) have become very important. As one of the DFM/DFY methods, a redundant via insertion technique uses as many vias as possible to connect the metal wires between different layers. In this paper, we focus on redundant vias and propose an effective redundant via insertion method for practical use to address the manufacturing variability and reliability concerns. First, the results of statistical analysis for via resistance and via capacitance in some real physical layouts are shown, and the impact on circuit delay of the resistance variation of vias caused by manufacturing variability is clarified. Then, the valuation functions of delay variation, electro-migration (EM), and stress-migration (SM) are defined and a practical method concerning redundant via insertion is proposed. Experimental results show that LSI with redundant vias inserted by our method robust against manufacturing variability and reliability problems.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.2962/_p
Salinan
@ARTICLE{e92-a_12_2962,
author={Yuji TAKASHIMA, Kazuyuki OOYA, Atsushi KUROKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability},
year={2009},
volume={E92-A},
number={12},
pages={2962-2970},
abstract={As the integrated circuit technology has undergone continuous downscaling to improve the LSI performance and reduce chip size, design for manufacturability (DFM) and design for yield (DFY) have become very important. As one of the DFM/DFY methods, a redundant via insertion technique uses as many vias as possible to connect the metal wires between different layers. In this paper, we focus on redundant vias and propose an effective redundant via insertion method for practical use to address the manufacturing variability and reliability concerns. First, the results of statistical analysis for via resistance and via capacitance in some real physical layouts are shown, and the impact on circuit delay of the resistance variation of vias caused by manufacturing variability is clarified. Then, the valuation functions of delay variation, electro-migration (EM), and stress-migration (SM) are defined and a practical method concerning redundant via insertion is proposed. Experimental results show that LSI with redundant vias inserted by our method robust against manufacturing variability and reliability problems.},
keywords={},
doi={10.1587/transfun.E92.A.2962},
ISSN={1745-1337},
month={December},}
Salinan
TY - JOUR
TI - Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2962
EP - 2970
AU - Yuji TAKASHIMA
AU - Kazuyuki OOYA
AU - Atsushi KUROKAWA
PY - 2009
DO - 10.1587/transfun.E92.A.2962
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2009
AB - As the integrated circuit technology has undergone continuous downscaling to improve the LSI performance and reduce chip size, design for manufacturability (DFM) and design for yield (DFY) have become very important. As one of the DFM/DFY methods, a redundant via insertion technique uses as many vias as possible to connect the metal wires between different layers. In this paper, we focus on redundant vias and propose an effective redundant via insertion method for practical use to address the manufacturing variability and reliability concerns. First, the results of statistical analysis for via resistance and via capacitance in some real physical layouts are shown, and the impact on circuit delay of the resistance variation of vias caused by manufacturing variability is clarified. Then, the valuation functions of delay variation, electro-migration (EM), and stress-migration (SM) are defined and a practical method concerning redundant via insertion is proposed. Experimental results show that LSI with redundant vias inserted by our method robust against manufacturing variability and reliability problems.
ER -